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SN54ALS04BJ PDF预览

SN54ALS04BJ

更新时间: 2024-11-03 22:59:11
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路
页数 文件大小 规格书
15页 516K
描述
HEX INVERTERS

SN54ALS04BJ 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP-14针数:14
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.87Is Samacsys:N
系列:ALSJESD-30 代码:R-GDIP-T14
长度:19.56 mm负载电容(CL):50 pF
逻辑集成电路类型:INVERTER最大I(ol):0.008 A
功能数量:6输入次数:1
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):4.4 mAProp。Delay @ Nom-Sup:17 ns
传播延迟(tpd):17 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.67 mm
Base Number Matches:1

SN54ALS04BJ 数据手册

 浏览型号SN54ALS04BJ的Datasheet PDF文件第2页浏览型号SN54ALS04BJ的Datasheet PDF文件第3页浏览型号SN54ALS04BJ的Datasheet PDF文件第4页浏览型号SN54ALS04BJ的Datasheet PDF文件第5页浏览型号SN54ALS04BJ的Datasheet PDF文件第6页浏览型号SN54ALS04BJ的Datasheet PDF文件第7页 
SN54ALS04B, SN54AS04, SN74ALS04B, SN74AS04  
HEX INVERTERS  
SDAS063B – APRIL 1982 – REVISED DECEMBER 1994  
SN54ALS04B, SN54AS04 . . . J PACKAGE  
SN74ALS04B, SN74AS04 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1Y  
2A  
2Y  
3A  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
6A  
6Y  
5A  
5Y  
4A  
4Y  
description  
These devices contain six independent hex  
inverters. They perform the Boolean function  
Y = A.  
3Y  
GND  
8
The SN54ALS04B and SN54AS04 are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS04B and SN74AS04 are characterized  
for operation from 0°C to 70°C.  
SN54ALS04B, SN54AS04 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each inverter)  
3
2
1
20 19  
18  
2A  
NC  
2Y  
4
5
6
7
8
6Y  
NC  
5A  
NC  
5Y  
INPUT  
A
OUTPUT  
Y
17  
16  
15  
14  
H
L
L
NC  
3A  
H
9 10 11 12 13  
NC – No internal connection  
logic symbol  
logic diagram (positive logic)  
1
1A  
3
2
4
1
2
1
1Y  
2Y  
3Y  
4Y  
5Y  
6Y  
1A  
1Y  
2Y  
3Y  
4Y  
5Y  
6Y  
2A  
5
6
3
4
6
3A  
9
2A  
8
4A  
11  
10  
12  
5
5A  
13  
3A  
6A  
9
8
4A  
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
11  
10  
12  
5A  
13  
6A  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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