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SN54AHCT373 PDF预览

SN54AHCT373

更新时间： 2024-11-24 23:06:07
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德州仪器 - TI 锁存器输出元件
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16页 532K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN54AHCT373 数据手册

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SN54AHCT373, SN74AHCT373  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS239M – OCTOBER 1995 – REVISED JULY 2003  
Inputs Are TTL-Voltage Compatible  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
– 1000-V Charged-Device Model (C101)  
SN54AHCT373 . . . J OR W PACKAGE  
SN74AHCT373 . . . DB, DGV, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54AHCT373 . . . FK PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
3
2
1 20 19  
18  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
4
5
6
7
8
17  
16  
15  
14 6D  
9 10 11 12 13  
GND  
description/ordering information  
The ’AHCT373 devices are octal-transparent D-type latches. When the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without  
interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74AHCT373N  
SN74AHCT373N  
Tube  
SN74AHCT373DW  
SN74AHCT373DWR  
SN74AHCT373NSR  
SN74AHCT373DBR  
SN74AHCT373PW  
SN74AHCT373PWR  
SOIC – DW  
AHCT373  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP – NS  
AHCT373  
HB373  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
HB373  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
SN74AHCT373DGVR HB373  
SNJ54AHCT373J  
SNJ54AHCT373W  
SNJ54AHCT373FK  
SNJ54AHCT373J  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHCT373W  
SNJ54AHCT373FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

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