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SN54AHC132J PDF预览

SN54AHC132J

更新时间： 2024-11-03 23:06:07
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路输入元件
页数 文件大小 规格书
8页 130K
描述
QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS

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SN54AHC132J 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：CERAMIC, DIP-14针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84Is Samacsys：N
系列：AHCJESD-30 代码：R-GDIP-T14
长度：19.56 mm逻辑集成电路类型：NAND GATE
功能数量：4输入次数：2
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：17.5 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3.3 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

SN54AHC132J 数据手册

 浏览型号SN54AHC132J的Datasheet PDF文件第2页浏览型号SN54AHC132J的Datasheet PDF文件第3页浏览型号SN54AHC132J的Datasheet PDF文件第4页浏览型号SN54AHC132J的Datasheet PDF文件第5页浏览型号SN54AHC132J的Datasheet PDF文件第6页浏览型号SN54AHC132J的Datasheet PDF文件第7页 
SN54AHC132, SN74AHC132  
QUADRUPLE POSITIVE-NAND GATES  
WITH SCHMITT-TRIGGER INPUTS  
SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002  
Operating Range 2-V to 5.5-V V  
Same Pinouts as ’AHC00  
CC  
Operation From Very Slow Input  
Transitions  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Temperature-Compensated Threshold  
Levels  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
High Noise Immunity  
– 1000-V Charged-Device Model (C101)  
SN54AHC132 . . . J OR W PACKAGE  
SN74AHC132 . . . D, DB, DGV, N, NS,  
OR PW PACKAGE  
SN54AHC132 . . . FK PACKAGE  
SN74AHC132 . . . RGY PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
(TOP VIEW)  
1
14  
3
2
1
20 19  
18  
1A  
1B  
V
CC  
4B  
14  
13  
1
2
3
4
5
6
7
4A  
17 NC  
1Y  
NC  
2A  
4
5
6
7
8
1B  
1Y  
2A  
2B  
2Y  
13 4B  
12 4A  
2
3
4
5
6
1Y  
12 4A  
16  
15  
14  
4Y  
NC  
3B  
11  
10  
9
4Y  
3B  
3A  
11  
10  
9
2A  
4Y  
3B  
3A  
3Y  
NC  
2B  
2B  
2Y  
9 10 11 12 13  
7
8
8
GND  
NC – No internal connection  
description/ordering information  
The ’AHC132 devices are quadruple positive-NAND gates designed for 2-V to 5.5-V V  
operation.  
CC  
These devices perform the Boolean function Y = A • B or Y = A + B in positive logic.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
QFN – RGY  
PDIP – N  
Tape and reel  
Tube  
SN74AHC132RGYR  
SN74AHC132N  
HA132  
SN74AHC132N  
Tube  
SN74AHC132D  
SOIC – D  
AHC132  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AHC132DR  
SN74AHC132NSR  
SN74AHC132DBR  
SN74AHC132PWR  
SN74AHC132DGVR  
SNJ54AHC132J  
–40°C to 85°C  
SOP – NS  
AHC132  
SSOP – DB  
TSSOP – PW  
TVSOP – DGV  
CDIP – J  
HA132  
HA132  
HA132  
SNJ54AHC132J  
SNJ54AHC132W  
SNJ54AHC132FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHC132W  
SNJ54AHC132FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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