SN74LVCZ161284A
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
www.ti.com
SCES358B–SEPTEMBER 2001–REVISED MAY 2005
FEATURES
DGG PACKAGE
(TOP VIEW)
•
Power-On Reset (POR) Prevents Printer
Errors When Printer Is Turned On, But No
Valid Signal Is at Pins A9–A13
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
HD
A9
DIR
Y9
2
•
•
Operates From 3 V to 3.6 V
3
A10
A11
A12
A13
Y10
Y11
Y12
Y13
1.4-kΩ Pullup Resistors Integrated on All
Open-Drain Outputs Eliminate the Need for
Discrete Resistors
4
5
6
•
Designed for IEEE Std 1284-I (Level-1 Type)
and IEEE Std 1284-II (Level-2 Type) Electrical
Specifications
7
V
V
CABLE
CC
CC
8
A1
A2
B1
B2
9
•
•
•
•
Flow-Through Architecture Optimizes PCB
Layout
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
A3
A4
GND
B3
B4
Ioff and Power-Up 3-State Support Hot
Insertion
A5
B5
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
A6
GND
A7
B6
GND
B7
B8
V
ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 350-V Machine Model (A115-A)
A8
V
CABLE
CC
CC
PERI LOGIC IN
PERI LOGIC OUT
C14
C15
C16
– 1500-V Charged-Device Model (C101)
A14
A15
A16
A17
DESCRIPTION/ORDERING INFORMATION
C17
The SN74LVCZ161284A is designed for 3-V to 3.6-V
VCC operation. This device provides asynchronous
two-way communication between data buses. The
control-function implementation minimizes external
timing requirements.
HOST LOGIC OUT
HOST LOGIC IN
This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control (DIR) input
is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side and
four receivers. The SN74LVCZ161284A has one receiver dedicated to the HOST LOGIC line and a driver to
drive the PERI LOGIC line.
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a
totem-pole configuration and in an open-drain configuration when HD is low. This meets the drive requirements
as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface
specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have
a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low
state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.
The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs
and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even
when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
LVCZ161284A
0°C to 70°C
TSSOP – DGG
Tape and reel
SN74LVCZ161284AGR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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