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SN54AC373-SP PDF预览

SN54AC373-SP

更新时间： 2024-11-26 11:07:07
品牌 Logo 应用领域
德州仪器 - TI 驱动锁存器总线驱动器总线收发器
页数 文件大小 规格书
19页 590K
描述
具有三态输出的八路 D 类透明锁存器

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SN54AC373-SP 数据手册

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SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003  
SN54AC373 . . . J OR W PACKAGE  
SN74AC373 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
2-V to 6-V V  
Operation  
CC  
Inputs Accept Voltages to 6 V  
Max t of 9.5 ns at 5 V  
pd  
3-State Noninverting Outputs Drive Bus  
Lines Directly  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
D
Full Parallel Access for Loading  
description/ordering information  
These 8-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. The devices  
are particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
GND  
SN54AC373 . . . FK PACKAGE  
(TOP VIEW)  
The eight latches are D-type transparent latches.  
When the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the logic  
levels set up at the D inputs.  
3
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
6D  
4
5
6
7
8
17  
16  
15  
14  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines in bus-organized systems without need for  
interface or pullup components.  
9 10 11 12 13  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
Tube  
SN74AC373N  
SN74AC373N  
Tube  
SN74AC373DW  
SN74AC373DWR  
SN74AC373NSR  
SN74AC373DBR  
SN74AC373PW  
SN74AC373PWR  
SNJ54AC373J  
SOIC − DW  
AC373  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
AC373  
AC373  
−40°C to 85°C  
−55°C to 125°C  
SSOP − DB  
TSSOP − PW  
AC373  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54AC373J  
SNJ54AC373W  
SNJ54AC373FK  
Tube  
SNJ54AC373W  
SNJ54AC373FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

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