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SN54ABT5403JT

更新时间： 2024-11-11 23:06:07
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路输出元件信息通信管理
页数 文件大小 规格书
6页 108K
描述
12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS

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SN54ABT5403JT 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：CERAMIC, DIP-28针数：28
Reach Compliance Code：unknown风险等级：5.84
Is Samacsys：N其他特性：WITH DUAL OUTPUT ENABLE
控制类型：ENABLE LOW系列：ABT
JESD-30 代码：R-GDIP-T28长度：36.83 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.008 A位数：12
功能数量：1端口数量：2
端子数量：28最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：INVERTED封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP28,.3
封装形状：RECTANGULAR封装形式：IN-LINE
电源：5 V最大电源电流（ICC）：45 mA
Prop。Delay @ Nom-Sup：7 ns传播延迟（tpd）：5.9 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：BICMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

SN54ABT5403JT 数据手册

 浏览型号SN54ABT5403JT的Datasheet PDF文件第2页浏览型号SN54ABT5403JT的Datasheet PDF文件第3页浏览型号SN54ABT5403JT的Datasheet PDF文件第4页浏览型号SN54ABT5403JT的Datasheet PDF文件第5页浏览型号SN54ABT5403JT的Datasheet PDF文件第6页 
SN54ABT5403, SN74ABT5403  
12-BIT LINE/MEMORY DRIVERS  
WITH 3-STATE OUTPUTS  
SCBS236B – JUNE 1992 – REVISED JANUARY 1997  
SN54ABT5403 . . . JT PACKAGE  
SN74ABT5403 . . . DW PACKAGE  
(TOP VIEW)  
Output Ports Have Equivalent 25-Ω Series  
Resistors, So No External Resistors Are  
Required  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
GND  
Y7  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
1
2
3
4
5
6
7
8
9
28  
27  
26  
25  
24  
23  
22  
21  
20  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
at V  
= 5 V, T = 25°C  
CC  
A
Typical V  
(Output Undershoot) < 0.5 V at  
OLV  
V
= 5 V, T = 25°C  
V
CC  
CC  
A
Y8  
D8  
Package Options Include Plastic  
Small-Outline (DW) Package, Ceramic Chip  
Carriers (FK), and DIPs (JT)  
Y9 10  
19 D9  
Y10  
Y11  
D10  
D11  
11  
12  
18  
17  
Y12 13  
OE1 14  
16 D12  
15 OE2  
description  
These 12-bit buffers and line drivers are designed  
specifically to improve both the performance and  
density of 3-state memory address drivers, clock  
drivers, and bus-oriented receivers and  
transmitters.  
SN54ABT5403 . . . FK PACKAGE  
(TOP VIEW)  
The 3-state control gate is a 2-input AND gate with  
active-low inputs so that if either output-enable  
(OE1or OE2)inputishigh, all12outputsareinthe  
high-impedance state. These devices provide  
inverted data.  
4
3
2
1
28 27 26  
25  
5
D3  
D2  
D1  
Y1  
Y2  
Y3  
Y4  
D10  
D11  
D12  
OE2  
OE1  
Y12  
Y11  
6
24  
23  
22  
21  
20  
19  
7
8
The outputs, which are designed to source or sink  
up to 12 mA, include equivalent 25-Ω series  
resistors to reduce overshoot and undershoot.  
9
10  
11  
12 13 14 15 16 17 18  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
CC  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
The SN54ABT5403 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ABT5403 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
OE1  
L
OE2  
L
D
L
H
L
L
L
H
X
X
H
X
Z
Z
X
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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