5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN54ABT16841WD
SN54ABT16841WD PDF预览

SN54ABT16841WD

更新时间： 2024-09-30 23:06:07
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路输出元件信息通信管理
页数 文件大小 规格书
7页 112K
描述
20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN54ABT16841WD 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DFP包装说明：0.380 INCH, FINE PITCH, CERAMIC, FP-56
针数：56Reach Compliance Code：not_compliant
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.88Is Samacsys：N
其他特性：TYP VOLP < 0.8V @ VCC = 5V, TA = 25 DEG C系列：ABT
JESD-30 代码：R-GDFP-F56长度：18.288 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.064 A位数：10
功能数量：2端口数量：2
端子数量：56最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装等效代码：FL56,.4,25
封装形状：RECTANGULAR封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
最大电源电流（ICC）：89 mAProp。Delay @ Nom-Sup：5.7 ns
传播延迟（tpd）：5.5 ns认证状态：Not Qualified
座面最大高度：3.05 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：MILITARY
端子形式：FLAT端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：9.652 mmBase Number Matches：1

SN54ABT16841WD 数据手册

 浏览型号SN54ABT16841WD的Datasheet PDF文件第2页浏览型号SN54ABT16841WD的Datasheet PDF文件第3页浏览型号SN54ABT16841WD的Datasheet PDF文件第4页浏览型号SN54ABT16841WD的Datasheet PDF文件第5页浏览型号SN54ABT16841WD的Datasheet PDF文件第6页浏览型号SN54ABT16841WD的Datasheet PDF文件第7页 
SN54ABT16841, SN74ABT16841  
20-BIT BUS-INTERFACE D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCBS222C – SEPTEMBER 1992 – REVISED MAY 1997  
SN54ABT16841 . . . WD PACKAGE  
SN74ABT16841 . . . DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
2
3
4
5
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
6
7
V
V
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
CC  
CC  
OLP  
8
1Q5  
1Q6  
1Q7  
GND  
1Q8  
1Q9  
1Q10  
2Q1  
2Q2  
2Q3  
GND  
2Q4  
2Q5  
2Q6  
1D5  
1D6  
1D7  
GND  
1D8  
1D9  
1D10  
2D1  
2D2  
2D3  
GND  
2D4  
2D5  
2D6  
= 5 V, T = 25°C  
CC  
A
9
High-Impedance State During Power Up  
and Power Down  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
Flow-Through Architecture Optimizes PCB  
Layout  
High-Drive Outputs (–32-mA I , 64-mA I  
)
OL  
OH  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) Package and  
380-mil Fine-Pitch Ceramic Flat (WD)  
Package Using 25-mil Center-to-Center  
Spacings  
V
V
CC  
CC  
description  
2Q7  
2Q8  
GND  
2Q9  
2Q10  
2OE  
2D7  
2D8  
GND  
2D9  
2D10  
2LE  
These 20-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
The ’ABT16841 can be used as two 10-bit latches or one 20-bit latch. The 20 transparent D-type latches provide  
true data at the outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding  
10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D  
inputs.  
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch  
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,  
the outputs neither load nor drive the bus lines significantly.  
The output-enable input does not affect the internal operation of the latches. Old data can be retained or new  
data can be entered while the outputs are in the high-impedance state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

中文翻译

下载PDF

与SN54ABT16841WD相关器件

型号 品牌 获取价格 描述 数据表
SN54ABT16843 TI

获取价格

 		18-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54ABT16843_08 TI

获取价格

 		18-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54ABT16843_13 TI

获取价格

 		18-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54ABT16843WD TI

获取价格

 		18-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54ABT16853 TI

获取价格

 		DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SN54ABT16853_06 TI

获取价格

 		DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SN54ABT16853_07 TI

获取价格

 		DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SN54ABT16853WD TI

获取价格

 		DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SN54ABT16862WDR TI

获取价格

 		ABT SERIES, DUAL 10-BIT TRANSCEIVER, INVERTED OUTPUT, CDFP56
SN54ABT16863 TI

获取价格

 		18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

与SN54ABT16841WD相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证