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SN54ABT16833

更新时间： 2024-11-13 23:06:07
品牌 Logo 应用领域
德州仪器 - TI 总线收发器
页数 文件大小 规格书
11页 191K
描述
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

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SN54ABT16833 数据手册

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SN54ABT16833, SN74ABT16833  
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS  
SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997  
SN54ABT16833 . . . WD PACKAGE  
SN74ABT16833 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1OEB  
1CLK  
1ERR  
GND  
1A1  
1OEA  
1CLR  
1PARITY  
GND  
1B1  
1B2  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
2
3
4
Typical V  
< 1 V at V  
(Output Ground Bounce)  
OLP  
CC  
5
= 5 V, T = 25°C  
A
1A2  
6
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
V
V
7
CC  
CC  
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
8
Flow-Through Architecture Optimizes  
PCB Layout  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
Parity-Error Flag With Parity  
Generator/Checker  
Register for Storage of Parity-Error Flag  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
V
V
CC  
CC  
The ’ABT16833 consist of two noninverting 8-bit  
to 9-bit parity bus transceivers and are designed  
for communication between data buses. For each  
transceiver, when data is transmitted from the  
A bus to the B bus, an odd-parity bit is generated  
and output on the parity I/O pin (1PARITY or  
2PARITY). When data is transmitted from the  
B bus to the A bus, 1PARITY (or 2PARITY) is  
configured as an input and combined with the  
B-input data to generate an active-low error flag if  
odd parity is not detected.  
2A7  
2A8  
GND  
2ERR  
2CLK  
2OEB  
2B7  
2B8  
GND  
2PARITY  
2CLR  
2OEA  
The error (1ERR or 2ERR) output is configured as an open-collector output. The B-to-A parity-error flag is  
clocked into 1ERR (or 2ERR) on the low-to-high transition of the clock (1CLK or 2CLK) input. 1ERR (or 2ERR)  
is cleared (set high) by taking the clear (1CLR or 2CLR) input low.  
The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively  
isolated. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity  
is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic  
capability.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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