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SN54ABT16825 PDF预览

SN54ABT16825

更新时间： 2024-11-13 23:06:07
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德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
6页 109K
描述
18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN54ABT16825 数据手册

 浏览型号SN54ABT16825的Datasheet PDF文件第2页浏览型号SN54ABT16825的Datasheet PDF文件第3页浏览型号SN54ABT16825的Datasheet PDF文件第4页浏览型号SN54ABT16825的Datasheet PDF文件第5页浏览型号SN54ABT16825的Datasheet PDF文件第6页 
SN54ABT16825, SN74ABT16825  
18-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCBS218C – JUNE 1992 – REVISED MAY 1997  
SN54ABT16825 . . . WD PACKAGE  
SN74ABT16825 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1OE1  
1Y1  
1Y2  
GND  
1Y3  
1Y4  
1OE2  
1A1  
1A2  
GND  
1A3  
1A4  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
2
3
4
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
5
at V  
= 5 V, T = 25°C  
CC  
A
6
High-Impedance State During Power Up  
and Power Down  
V
V
7
CC  
CC  
1Y5  
1Y6  
1Y7  
GND  
1Y8  
1A5  
1A6  
1A7  
GND  
1A8  
8
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
9
10  
11  
12  
Flow-Through Architecture Optimizes PCB  
Layout  
High-Drive Outputs (–32-mA I , 64-mA I  
)
OL  
1Y9 13  
GND 14  
GND 15  
2Y1 16  
44 1A9  
43 GND  
42 GND  
41 2A1  
OH  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
2Y2  
GND  
2Y3  
2Y4  
2Y5  
2A2  
GND  
2A3  
2A4  
2A5  
description  
The ’ABT16825 are 18-bit buffers and line drivers  
designed specifically to improve both the  
performance and density of 3-state memory  
address drivers, clock drivers, and bus-oriented  
receivers and transmitters. These devices can be  
used as two 9-bit buffers or one 18-bit buffer. They  
provide true data.  
V
V
CC  
CC  
2Y6  
2Y7  
GND  
2Y8  
2Y9  
2A6  
2A7  
GND  
2A8  
2A9  
2OE1  
2OE2  
The 3-state control gate is a 2-input AND gate with  
active-low inputs so that if either output-enable  
(OE1 or OE2) input is high, all nine affected  
outputs are in the high-impedance state.  
When V  
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
The SN54ABT16825 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ABT16825 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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