5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN54ABT16646
SN54ABT16646 PDF预览

SN54ABT16646

更新时间： 2024-09-30 23:06:07
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
15页 245K
描述
16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN54ABT16646 数据手册

 浏览型号SN54ABT16646的Datasheet PDF文件第2页浏览型号SN54ABT16646的Datasheet PDF文件第3页浏览型号SN54ABT16646的Datasheet PDF文件第4页浏览型号SN54ABT16646的Datasheet PDF文件第5页浏览型号SN54ABT16646的Datasheet PDF文件第6页浏览型号SN54ABT16646的Datasheet PDF文件第7页 
SN54ABT16646, SN74ABT16646  
16-BIT BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCBS212D – JUNE 1992 – REVISED JULY 1999  
SN54ABT16646 . . . WD PACKAGE  
SN74ABT16646 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1DIR  
1CLKAB  
1SAB  
GND  
1OE  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
2
1CLKBA  
1SBA  
GND  
1B1  
3
4
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
5
1A1  
1A2  
at V  
= 5 V, T = 25°C  
CC  
A
6
1B2  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
7
V
V
CC  
CC  
8
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
Flow-Through Architecture Optimizes PCB  
Layout  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
The  
’ABT16646  
devices  
consist  
of  
bus-transceiver circuits, D-type flip-flops, and  
control circuitry arranged for multiplexed  
transmission of data directly from the input bus or  
from the internal registers.  
V
V
CC  
CC  
2A7  
2A8  
GND  
2B7  
2B8  
GND  
2SBA  
2CLKBA  
2OE  
These devices can be used as two 8-bit  
transceivers or one 16-bit transceiver. Data on the  
A or B bus is clocked into the registers on the  
low-to-high transition of the appropriate clock  
(CLKAB or CLKBA) input. Figure 1 illustrates the  
four fundamental bus-management functions that  
can be performed with the ’ABT16646 devices.  
2SAB  
2CLKAB  
2DIR  
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the  
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The  
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry  
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition  
between stored and real-time data. The direction control (DIR) determines which bus receives data when OE  
is low. In the isolation mode (OE high), A data can be stored in one register and/or B data can be stored in the  
other register.  
When an output function is disabled, the input function is still enabled and can be used to store and transmit  
data. Only one of the two buses, A or B, can be driven at a time.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

中文翻译

下载PDF

SN54ABT16646 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT16646 TI

功能相似

 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

与SN54ABT16646相关器件

型号 品牌 获取价格 描述 数据表
SN54ABT16646_08 TI

获取价格

 		16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54ABT16646WD TI

获取价格

 		16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54ABT16648WD TI

获取价格

 		ABT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, CDFP56
SN54ABT16652 TI

获取价格

 		16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54ABT16652_07 TI

获取价格

 		16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54ABT16652_08 TI

获取价格

 		16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54ABT16652WD TI

获取价格

 		16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54ABT16657 TI

获取价格

 		16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SN54ABT16657_08 TI

获取价格

 		16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SN54ABT16657WD TI

获取价格

 		16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS

与SN54ABT16646相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证