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SN54ABT162841WD PDF预览

SN54ABT162841WD

更新时间： 2024-09-12 23:06:07
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
8页 133K
描述
20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

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中文翻译

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SN54ABT162841WD 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP, FL56,.4,25针数：56
Reach Compliance Code：unknown风险等级：5.84
系列：ABTJESD-30 代码：R-GDFP-F56
长度：18.288 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.008 A
位数：10功能数量：2
端口数量：2端子数量：56
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装等效代码：FL56,.4,25封装形状：RECTANGULAR
封装形式：FLATPACK电源：5 V
最大电源电流（ICC）：89 mAProp。Delay @ Nom-Sup：6.2 ns
传播延迟（tpd）：6.1 ns认证状态：Not Qualified
座面最大高度：3.05 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：MILITARY
端子形式：FLAT端子节距：0.635 mm
端子位置：DUAL宽度：9.652 mm
Base Number Matches：1

SN54ABT162841WD 数据手册

 浏览型号SN54ABT162841WD的Datasheet PDF文件第2页浏览型号SN54ABT162841WD的Datasheet PDF文件第3页浏览型号SN54ABT162841WD的Datasheet PDF文件第4页浏览型号SN54ABT162841WD的Datasheet PDF文件第5页浏览型号SN54ABT162841WD的Datasheet PDF文件第6页浏览型号SN54ABT162841WD的Datasheet PDF文件第7页 
SN54ABT162841, SN74ABT162841  
20-BIT BUS-INTERFACE D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCBS665B – JUNE 1996 – REVISED MAY 1997  
SN54ABT162841 . . . WD PACKAGE  
SN74ABT162841 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
Output Ports Have Equivalent 25-Ω Series  
Resistors, So No External Resistors Are  
Required  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
2
3
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
4
5
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
6
7
V
V
CC  
CC  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
8
1Q5  
1Q6  
1Q7  
GND  
1Q8  
1Q9  
1Q10  
2Q1  
2Q2  
2Q3  
GND  
2Q4  
2Q5  
2Q6  
1D5  
1D6  
1D7  
GND  
1D8  
1D9  
1D10  
2D1  
2D2  
2D3  
GND  
2D4  
2D5  
2D6  
= 5 V, T = 25°C  
CC  
A
9
High-Impedance State During Power Up  
and Power Down  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
Flow-Through Architecture Optimizes PCB  
Layout  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL), Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
V
V
description  
CC  
CC  
2Q7  
2Q8  
GND  
2Q9  
2Q10  
2OE  
2D7  
2D8  
GND  
2D9  
2D10  
2LE  
These 20-bit transparent D-type latches feature  
noninverting 3-state outputs designed specifically  
for driving highly capacitive or relatively  
low-impedance loads. They are particularly  
suitable for implementing buffer registers, I/O  
ports, bidirectional bus drivers, and working  
registers.  
The ’ABT162841 can be used as two 10-bit latches or one 20-bit latch. While the latch-enable (1LE or 2LE) input  
is high, the Q outputs of the corresponding 10-bit latch follow the data (D) inputs. When LE is taken low, the  
Q outputs are latched at the levels set up at the D inputs.  
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch  
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,  
the outputs neither load nor drive the bus lines significantly.  
The outputs, which are designed to sink up to 12 mA, include equivalent 25-Ω series resistors to reduce  
overshoot and undershoot.  
OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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