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SN54ABT162827 PDF预览

SN54ABT162827

更新时间： 2024-09-13 12:47:03
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
10页 188K
描述
20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN54ABT162827 数据手册

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SCBS248B − JULY 1993 − REVISED DECEMBER 1994  
SN54ABT162827 . . . WD PACKAGE  
SN74ABT162827 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
• Output Ports Have Equivalent 25-Ω Series  
Resistors, So No External Resistors Are  
Required  
• Members of the Texas Instruments  
1OE1  
1Y1  
1Y2  
GND  
1Y3  
1Y4  
1OE2  
1A1  
1A2  
GND  
1A3  
A14  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
52  
51  
50  
49  
48  
WidebusFamily  
• State-of-the-Art EPIC-ΙΙBBiCMOS Design  
Significantly Reduces Power Dissipation  
• Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
V
V
• Typical V  
(Output Ground Bounce)  
CC  
CC  
OLP  
CC  
1Y5  
1Y6  
1A5  
1A6  
< 1 V at V  
= 5 V, T = 25°C  
A
• Distributed V  
and GND Pin Configuration  
Minimizes High-Speed Switching Noise  
CC  
1Y7 10  
GND  
1Y8  
47 1A7  
GND  
1A8  
11  
12  
46  
45  
• Flow-Through Architecture Optimizes  
PCB Layout  
1Y9 13  
1Y10 14  
2Y1 15  
2Y2 16  
2Y3 17  
GND 18  
2Y4 19  
2Y5 20  
2Y6 21  
44 1A9  
43 1A10  
42 2A1  
41 2A2  
40 2A3  
39 GND  
38 2A4  
37 2A5  
36 2A6  
• Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
The ′ABT162827 are noninverting 20-bit buffers  
composed of two 10-bit buffers with separate  
output-enable signals. For either 10-bit buffer, the  
two output-enable (1OE1 and 1OE2 or 2OE1 and  
2OE2) inputs must both be low for the  
corresponding Y outputs to be active. If either  
output-enable input is high, the outputs of that  
10-bit buffer are in the high-impedance state.  
V
22  
35  
V
CC  
CC  
2Y7 23  
34 2A7  
33 2A8  
32 GND  
31 2A9  
30 2A10  
29 2OE2  
2Y8 24  
GND 25  
2Y9 26  
2Y10 27  
2OE1 28  
The outputs, which are designed to source or sink  
up to 12 mA, include 25-Ω series resistors to  
reduce overshoot and undershoot.  
To ensure the high-impedance state during power up or power down, OE inputs should be tied to V  
a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through  
CC  
The SN74ABT162827 is available in TI’s shrink small-outline package (DL), which provides twice the I/O pin  
count and functionality of standard small-outline packages in the same printed-circuit-board area.  
The SN54ABT162827 is characterized for operation over the full military temperature range of −55°C to 125°C.  
The SN74ABT162827 is characterized for operation from −40°C to 85°C.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1994, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...10

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