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SN54ABT162823A_15

更新时间： 2024-09-14 02:58:43
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德州仪器 - TI 输出元件
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8页 137K
描述
18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN54ABT162823A_15 数据手册

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SN54ABT162823A, SN74ABT162823A  
18-BIT BUS-INTERFACE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCBS666A – JULY 1996 – REVISED MAY 1997  
SN54ABT162823A . . . WD PACKAGE  
SN74ABT162823A . . . DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
Output Ports Have Equivalent 25-Ω Series  
Resistors So No External Resistors Are  
Required  
1CLR  
1OE  
1Q1  
GND  
1Q2  
1Q3  
1CLK  
1CLKEN  
1D1  
GND  
1D2  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
2
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
3
4
High-Impedance State During Power Up  
and Power Down  
5
1D3  
6
V
V
7
Typical V  
(Output Ground Bounce) < 1 V  
CC  
CC  
OLP  
1Q4  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
1Q9  
2Q1  
2Q2  
2Q3  
GND  
2Q4  
2Q5  
2Q6  
1D4  
1D5  
1D6  
GND  
1D7  
1D8  
1D9  
2D1  
2D2  
2D3  
GND  
2D4  
2D5  
2D6  
8
at V  
= 5 V, T = 25°C  
CC  
A
9
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Flow-Through Architecture Optimizes PCB  
Layout  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) Package and  
380-mil Fine-Pitch Ceramic Flat (WD)  
Package Using 25-mil Center-to-Center  
Spacings  
description  
These 18-bit bus-interface flip-flops feature  
3-state outputs designed specifically for driving  
highly capacitive or relatively low-impedance  
loads. They are particularly suitable for  
implementing wider buffer registers, I/O ports,  
bidirectional bus drivers with parity, and working  
registers.  
V
V
CC  
CC  
2Q7  
2Q8  
GND  
2Q9  
2OE  
2CLR  
2D7  
2D8  
GND  
2D9  
2CLKEN  
2CLK  
The ’ABT162823A can be used as two 9-bit  
flip-flops or one 18-bit flip-flop. With the  
clock-enable (CLKEN) input low, the D-type  
flip-flops enter data on the low-to-high transitions  
of the clock. Taking CLKEN high disables the  
clock buffer, thus latching the outputs. Taking the  
clear (CLR) input low causes the Q outputs to go  
low independently of the clock.  
A buffered output-enable (OE) input places the nine outputs in either a normal logic state (high or low level) or  
a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without  
interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be  
retained or new data can be entered while the outputs are in the high-impedance state.  
The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to  
reduce overshoot and undershoot.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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