是否Rohs认证: | 不符合 | 生命周期: | Obsolete |
零件包装代码: | DFP | 包装说明: | DFP, FL14,.3 |
针数: | 14 | Reach Compliance Code: | not_compliant |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.81 |
其他特性: | 3-IN AND GATED J/K INPUTS; PRESET/CLEAR ACTIVE ONLY WHEN CLOCK IS LOW | 系列: | TTL/H/L |
JESD-30 代码: | R-CDFP-F14 | 长度: | 8.725 mm |
负载电容(CL): | 15 pF | 逻辑集成电路类型: | J-K FLIP-FLOP |
位数: | 2 | 功能数量: | 1 |
端子数量: | 14 | 最高工作温度: | 125 °C |
最低工作温度: | -55 °C | 输出极性: | COMPLEMENTARY |
封装主体材料: | CERAMIC, METAL-SEALED COFIRED | 封装代码: | DFP |
封装等效代码: | FL14,.3 | 封装形状: | RECTANGULAR |
封装形式: | FLATPACK | 峰值回流温度(摄氏度): | NOT SPECIFIED |
最大电源电流(ICC): | 26 mA | 传播延迟(tpd): | 50 ns |
认证状态: | Not Qualified | 座面最大高度: | 2.03 mm |
子类别: | FF/Latches | 最大供电电压 (Vsup): | 5.5 V |
最小供电电压 (Vsup): | 4.5 V | 标称供电电压 (Vsup): | 5 V |
表面贴装: | YES | 技术: | TTL |
温度等级: | MILITARY | 端子形式: | FLAT |
端子节距: | 1.27 mm | 端子位置: | DUAL |
处于峰值回流温度下的最长时间: | NOT SPECIFIED | 触发器类型: | POSITIVE EDGE |
宽度: | 6.35 mm | 最小 fmax: | 20 MHz |
Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
SN5470W-00 | TI |
获取价格 |
TTL/H/L SERIES, POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14, CERAM | |
SN5470W-10 | TI |
获取价格 |
TTL/H/L SERIES, POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14, CERAM | |
SN5472 | TI |
获取价格 |
AND-GATED J-K MASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR | |
SN5472_14 | TI |
获取价格 |
AND-GATED J-K MASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR | |
SN5472F | ROCHESTER |
获取价格 |
J-K Flip-Flop | |
SN5472J | TI |
获取价格 |
AND-GATED J-K MASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR | |
SN5472J | ROCHESTER |
获取价格 |
J-K Flip-Flop, TTL/H/L Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Outpu | |
SN5472J-00 | TI |
获取价格 |
TTL/H/L SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 | |
SN5472W | TI |
获取价格 |
AND-GATED J-K MASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR | |
SN5472W-00 | TI |
获取价格 |
TTL/H/L SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14 |