是否无铅: | 含铅 | 是否Rohs认证: | 不符合 |
生命周期: | Obsolete | Reach Compliance Code: | not_compliant |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.59 |
Is Samacsys: | N | 其他特性: | 3-IN AND GATED J/K INPUTS; PRESET/CLEAR ACTIVE ONLY WHEN CLOCK IS LOW |
系列: | TTL/H/L | JESD-30 代码: | R-CDIP-T14 |
长度: | 19.56 mm | 负载电容(CL): | 15 pF |
逻辑集成电路类型: | J-K FLIP-FLOP | 位数: | 2 |
功能数量: | 1 | 端子数量: | 14 |
最高工作温度: | 125 °C | 最低工作温度: | -55 °C |
输出极性: | COMPLEMENTARY | 封装主体材料: | CERAMIC, METAL-SEALED COFIRED |
封装代码: | DIP | 封装等效代码: | DIP14,.3 |
封装形状: | RECTANGULAR | 封装形式: | IN-LINE |
峰值回流温度(摄氏度): | NOT SPECIFIED | 最大电源电流(ICC): | 26 mA |
传播延迟(tpd): | 50 ns | 认证状态: | Not Qualified |
座面最大高度: | 5.08 mm | 子类别: | FF/Latches |
最大供电电压 (Vsup): | 5.5 V | 最小供电电压 (Vsup): | 4.5 V |
标称供电电压 (Vsup): | 5 V | 表面贴装: | NO |
技术: | TTL | 温度等级: | MILITARY |
端子形式: | THROUGH-HOLE | 端子节距: | 2.54 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | NOT SPECIFIED |
触发器类型: | POSITIVE EDGE | 宽度: | 7.62 mm |
最小 fmax: | 20 MHz | Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
SN5470J-00 | TI |
获取价格 |
TTL/H/L SERIES, POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAM | |
SN-5470OHM0.01% | VISHAY |
获取价格 |
Fixed Resistor, Wire Wound, 4W, 470ohm, 212V, 0.01% +/-Tol, 20ppm/Cel, Surface Mount, 8230 | |
SN-5470OHM5% | VISHAY |
获取价格 |
Fixed Resistor, Wire Wound, 4W, 470ohm, 212V, 5% +/-Tol, 20ppm/Cel, Surface Mount, 8230, C | |
SN5470W | TI |
获取价格 |
AND-GATED J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | |
SN5470W-00 | TI |
获取价格 |
TTL/H/L SERIES, POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14, CERAM | |
SN5470W-10 | TI |
获取价格 |
TTL/H/L SERIES, POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14, CERAM | |
SN5472 | TI |
获取价格 |
AND-GATED J-K MASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR | |
SN5472_14 | TI |
获取价格 |
AND-GATED J-K MASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR | |
SN5472F | ROCHESTER |
获取价格 |
J-K Flip-Flop | |
SN5472J | TI |
获取价格 |
AND-GATED J-K MASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR |