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SN5470J PDF预览

SN5470J

更新时间: 2024-11-20 22:53:39
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路输入元件
页数 文件大小 规格书
5页 147K
描述
AND-GATED J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

SN5470J 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:ObsoleteReach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.59
Is Samacsys:N其他特性:3-IN AND GATED J/K INPUTS; PRESET/CLEAR ACTIVE ONLY WHEN CLOCK IS LOW
系列:TTL/H/LJESD-30 代码:R-CDIP-T14
长度:19.56 mm负载电容(CL):15 pF
逻辑集成电路类型:J-K FLIP-FLOP位数:2
功能数量:1端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED最大电源电流(ICC):26 mA
传播延迟(tpd):50 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:20 MHzBase Number Matches:1

SN5470J 数据手册

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SN5470, SN7470  
AND-GATED J-K POSITIVE-EDGE-TRIGGERED  
FLIP-FLOPS WITH PRESET AND CLEAR  
SDLS116 – DECEMBER 1983 – REVISED MARCH 1988  
Copyright 1988, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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