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SN54273_16 PDF预览

SN54273_16

更新时间: 2024-11-20 02:58:47
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德州仪器 - TI /
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6页 98K
描述
OCTAL D-TYPE FLIP-FLOP WITH CLEAR

SN54273_16 数据手册

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SN54273, SN54LS273, SN74273, SN74LS273  
OCTAL D-TYPE FLIP-FLOP WITH CLEAR  
SDLS090 – OCTOBER 1976 – REVISED MARCH 1988  
SN54273, SN74LS273 . . . J OR W PACKAGE  
SN74273 . . . N PACKAGE  
Contains Eight Flip-Flops With Single-Rail  
Outputs  
SN74LS273 . . . DW OR N PACKAGE  
(TOP VIEW)  
Buffered Clock and Direct Clear Inputs  
Individual Data Input to Each Flip-Flop  
Applications Include:  
Buffer/Storage Registers  
Shift Registers  
CLR  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
8Q  
8D  
7D  
Pattern Generators  
16 7Q  
15 6Q  
description  
14  
13  
12  
11  
6D  
5D  
5Q  
CLK  
These monolithic, positive-edge-triggered flip-  
flops utilize TTL circuitry to implement D-type  
flip-flop logic with a direct clear input.  
GND  
Information at the D inputs meeting the setup time  
requirements is transferred to the Q outputs on the  
positive-going edge of the clock pulse. Clock  
triggering occurs at a particular voltage level and  
is not directly related to the transition time of the  
positive-going pulse. When the clock input is at  
either the high or low level, the D input signal has  
no effect ar the output.  
SN54LS273 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
These flip-flops are guaranteed to respond to  
clock frequencies ranging form 0 to 30 megahertz  
while maximum clock frequency is typically 40  
megahertz. Typical power dissipation is 39  
milliwatts per flip-flop for the 273 and 10 milliwatts  
for the LS273.  
17  
16  
15  
14  
9 10 11 12 13  
FUNCTION TABLE  
(each flip-flop)  
logic symbol  
INPUTS  
1
CLR  
OUTPUT  
Q
EN  
C1  
CLEAR CLOCK  
D
X
H
L
11  
CLK  
L
H
H
H
X
L
H
L
3
1D  
4
2
5
6
1D  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
2D  
7
L
X
Q
0
3D  
8
9
4D  
13  
5D  
14  
6D  
17  
7D  
18  
8D  
12  
15  
16  
19  
This symbol is in accordance with ANSI/IEEE Std.  
91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the DW, J, N, and W packages.  
Copyright 1988, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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