Datasheet > SN54173W-00

SN54173W-00

更新时间： 2024-11-16 20:57:23

品牌	Logo	应用领域
德州仪器 - TI		输出元件逻辑集成电路触发器
页数	文件大小	规格书
19页	529K
描述
TTL/H/L SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP16, CERAMIC, FP-16

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SN54173W-00 技术参数

生命周期：	Obsolete	零件包装代码：	DFP
包装说明：	DFP,	针数：	16
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.71	其他特性：	WITH HOLD MODE
系列：	TTL/H/L	JESD-30 代码：	R-GDFP-F16
长度：	10.16 mm	负载电容（CL）：	50 pF
逻辑集成电路类型：	D FLIP-FLOP	位数：	4
功能数量：	1	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-55 °C
输出特性：	3-STATE	输出极性：	TRUE
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK
最大电源电流（ICC）：	72 mA	传播延迟（tpd）：	31 ns
认证状态：	Not Qualified	座面最大高度：	2.03 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	TTL	温度等级：	MILITARY
端子形式：	FLAT	端子节距：	1.27 mm
端子位置：	DUAL	触发器类型：	POSITIVE EDGE
宽度：	6.73 mm	最小 fmax：	25 MHz
Base Number Matches：	1

SN54173W-00 数据手册

SN54173, SN54LS173A, SN74173, SN74LS173A

4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTS

SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

SN54173, SN54LS173A . . . J OR W PACKAGE

SN74173 . . . N PACKAGE

3-State Outputs Interface Directly With

System Bus

SN74LS173A . . . D or N PACKAGE

(TOP VIEW)

Gated Output-Control LInes for Enabling or

Disabling the Outputs

Fully Independent Clock Virtually

Eliminates Restrictions for Operating in

One of Two Modes:

– Parallel Load

– Do Nothing (Hold)

CLR

For Application as Bus Buffer Registers

CLK

GND

Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Flat

(W) Packages, Ceramic Chip Carriers (FK),

and Standard Plastic (N) and Ceramic (J)

DIPs

SN54LS173A . . . FK PACKAGE

(TOP VIEW)

TYPICAL

PROPAGATION

DELAY TIME

MAXIMUM

CLOCK

FREQUENCY

TYPE

1 20 19

’173

23 ns

18 ns

35 MHz

50 MHz

’LS173A

description

9 10 11 12 13

The ’173 and ’LS173A 4-bit registers include

D-type flip-flops featuring totem-pole 3-state

outputs capable of driving highly capacitive

or relatively low-impedance loads. The

high-impedance third state and increased

high-logic-level drive provide these flip-flops with

the capability of being connected directly to and

NC – No internal connection

driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of

the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or

54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can

be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load,

respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic

levels, the output control circuitry is designed so that the average output disable times are shorter than the

average output enable times.

Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both

data-enable (G1, G2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next

positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both

are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus

lines. The outputs are disabled independently from the level of the clock by a high logic level at either

output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed

operation is given in the function table.

The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of

–55°C to 125°C. The SN74173 and SN74LS173A are characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...19

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与SN54173W-00相关器件

型号	品牌	获取价格	描述	数据表
SN54173W-10	TI	获取价格	TTL/H/L SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP16, CERAMIC, FP-16
SN54174	TI	获取价格	HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SN54174_16	TI	获取价格	HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SN54174FK	TI	获取价格	TTL/H/L SERIES, HEX POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20, CERAMIC, CC-
SN54174J	TI	获取价格	HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SN54174W	TI	获取价格	HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SN54174W	ROCHESTER	获取价格	D Flip-Flop, TTL/H/L Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, TTL, CDF
SN54175	TI	获取价格	HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SN54175FK	TI	获取价格	TTL/H/L SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20, CERAMIC
SN54175J	TI	获取价格	HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

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