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SMUN2214T1 PDF预览

SMUN2214T1

更新时间: 2024-09-17 06:56:39
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
19页 221K
描述
100mA, 50V, NPN, Si, SMALL SIGNAL TRANSISTOR, CASE 318D-04, SC-59, 3 PIN

SMUN2214T1 数据手册

 浏览型号SMUN2214T1的Datasheet PDF文件第2页浏览型号SMUN2214T1的Datasheet PDF文件第3页浏览型号SMUN2214T1的Datasheet PDF文件第4页浏览型号SMUN2214T1的Datasheet PDF文件第5页浏览型号SMUN2214T1的Datasheet PDF文件第6页浏览型号SMUN2214T1的Datasheet PDF文件第7页 
MUN2211T1, SMUN2211T1,  
NSVMUN2211T1 Series  
Bias Resistor Transistors  
NPN Silicon Surface Mount Transistors  
with Monolithic Bias Resistor Network  
http://onsemi.com  
This new series of digital transistors is designed to replace a single  
device and its external resistor bias network. The BRT (Bias Resistor  
Transistor) contains a single transistor with a monolithic bias network  
consisting of two resistors; a series base resistor and a baseemitter  
resistor. The BRT eliminates these individual components by  
integrating them into a single device. The use of a BRT can reduce  
both system cost and board space. The device is housed in the  
SC59 package which is designed for low power surface  
mount applications.  
NPN SILICON  
BIAS RESISTOR  
TRANSISTORS  
Features  
SC59  
CASE 318D  
STYLE 1  
Simplifies Circuit Design  
Reduces Board Space  
Reduces Component Count  
PIN 3  
COLLECTOR  
(OUTPUT)  
Moisture Sensitivity Level: 1  
PIN 2  
BASE  
(INPUT)  
R
R
1
ESD Rating Human Body Model: Class 1  
Machine Model: Class B  
2
PIN 1  
EMITTER  
(GROUND)  
The SC59 Package can be Soldered Using Wave or Reflow  
The Modified GullWinged Leads Absorb Thermal Stress During  
Soldering Eliminating the Possibility of Damage to the Die  
AECQ101 Qualified and PPAP Capable  
MARKING DIAGRAM  
S and NSV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements  
PbFree Packages are Available*  
8x M G  
G
1
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
A
8x = Device Code (Refer to page 2)  
Rating  
Collector-Base Voltage  
Collector-Emitter Voltage  
Collector Current  
Symbol  
Value  
50  
Unit  
Vdc  
M
= Date Code*  
V
CBO  
CEO  
G
= PbFree Package  
V
50  
Vdc  
(Note: Microdot may be in either location)  
*Date Code orientation may vary depending  
upon manufacturing location.  
I
C
100  
mAdc  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the table on  
page 2 of this data sheet.  
DEVICE MARKING INFORMATION  
See specific marking information in the Device Marking and  
Resistor Values table on page 2 of this data sheet.  
Preferred devices are recommended choices for future use  
and best overall value.  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2012  
1
Publication Order Number:  
January, 2012 Rev. 15  
MUN2211T1/D  

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