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SMQ320C50PQM66 PDF预览

SMQ320C50PQM66

更新时间: 2024-11-24 22:21:39
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路数字信号处理器装置时钟
页数 文件大小 规格书
31页 484K
描述
DIGITAL SIGNAL PROCESSOR

SMQ320C50PQM66 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:PLASTIC, QFP-132针数:132
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.31.00.01风险等级:5.57
Is Samacsys:N地址总线宽度:16
桶式移位器:NO位大小:16
边界扫描:YES最大时钟频率:66 MHz
外部数据总线宽度:16格式:FIXED POINT
集成缓存:NO内部总线架构:MULTIPLE
JESD-30 代码:S-PQFP-G132长度:24.13 mm
低功率模式:YESDMA 通道数量:
外部中断装置数量:6串行 I/O 数:1
端子数量:132计时器数量:1
片上数据RAM宽度:16片上程序ROM宽度:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:BQFP
封装等效代码:SPQFP132,1.1SQ封装形状:SQUARE
封装形式:FLATPACK, BUMPER电源:5 V
认证状态:Not QualifiedRAM(字数):1056
ROM可编程性:MROM筛选级别:MIL-PRF-38535
座面最大高度:4.57 mm子类别:Digital Signal Processors
最大压摆率:225 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:0.635 mm端子位置:QUAD
宽度:24.13 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

SMQ320C50PQM66 数据手册

 浏览型号SMQ320C50PQM66的Datasheet PDF文件第2页浏览型号SMQ320C50PQM66的Datasheet PDF文件第3页浏览型号SMQ320C50PQM66的Datasheet PDF文件第4页浏览型号SMQ320C50PQM66的Datasheet PDF文件第5页浏览型号SMQ320C50PQM66的Datasheet PDF文件第6页浏览型号SMQ320C50PQM66的Datasheet PDF文件第7页 
SMJ320C50/SMQ320C50  
DIGITAL SIGNAL PROCESSOR  
SGUS020 – JUNE 1996  
HFG PACKAGE  
(TOP VIEW)  
Military Operating Temperature Range:  
– 55°C to 125°C  
Processed to MIL-PRF-38535  
Fast Instruction Cycle Time (30 ns and  
40 ns)  
1
99  
Source-Code Compatible With All ’C1x  
and ’C2x Devices  
RAM-Based Operation  
– 9K × 16-Bit Single-Cycle On-Chip  
Program/Data RAM  
– 1056 × 16-Bit Dual-Access On-Chip  
Data RAM  
33  
67  
2K × 16-Bit On-Chip Boot ROM  
224K × 16-Bit Maximum Addressable  
External Memory Space (64K Program,  
64K Data, 64K I/O, and 32K Global)  
GFA PACKAGE  
(TOP VIEW)  
32-Bit Arithmetic Logic Unit (ALU)  
– 32-bit Accumulator (ACC)  
– 32-Bit Accumulator Buffer (ACCB)  
A
C
B
D
F
E
G
J
16-Bit Parallel Logic Unit (PLU)  
16 × 16-Bit Multiplier, 32-Bit Product  
11 Context-Switch Registers  
H
K
L
M
P
T
Two Buffers for Circular Addressing  
Full-Duplex Synchronous Serial Port  
Time-Division Multiplexed Serial Port (TDM)  
Timer With Control and Counter Registers  
N
R
U
W
V
2
4
6
8 10 12 14 16 18  
11 13 15 17 19  
1
3
5
7
9
16 Software Programmable Wait-State  
Generators  
PQ PACKAGE  
(TOP VIEW)  
Divide-by-One Clock Option  
1 132  
117  
17  
IEEE 1149.1 Boundary Scan Logic  
Operations Are Fully Static  
18  
116  
Enhanced Performance Implanted CMOS  
(EPIC ) 0.72-µm Technology Fabricated by  
Texas Instruments  
Packaging  
– 141-Pin Ceramic Grid Array (GFA Suffix)  
– 132-Lead Ceramic Quad Flat Package  
(HFG Suffix)  
– 132-Lead Plastic Quad Flat Package  
(PQ Suffix)  
84  
50  
51  
83  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture  
EPIC and TI are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443  

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