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SM3603T-7.5 PDF预览

SM3603T-7.5

更新时间: 2024-01-23 06:37:42
品牌 Logo 应用领域
铁电 - RAMTRON 时钟动态存储器光电二极管内存集成电路
页数 文件大小 规格书
10页 108K
描述
Synchronous DRAM, 8MX8, 4.6ns, CMOS, PDSO54, TSOP2-54

SM3603T-7.5 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:SOP, TSOP54,.46,32针数:54
Reach Compliance Code:unknown风险等级:5.83
访问模式:FOUR BANK PAGE BURST最长访问时间:4.8 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:R-PDSO-G54
JESD-609代码:e0内存密度:67108864 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:8
功能数量:1端口数量:1
端子数量:54字数:8388608 words
字数代码:8000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:8MX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:TSOP54,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
刷新周期:4096自我刷新:YES
最大待机电流:0.0025 A子类别:DRAMs
最大压摆率:0.17 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

SM3603T-7.5 数据手册

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64Mbit – High Speed SDRAM  
Data Sheet  
8Mx8, 4Mx16 HSDRAM  
Features  
Description  
JEDEC Standard PC-133 SDRAM  
Fast 4.6 ns CL3 Clock Access Time  
Fast 13.75 ns CL1 Clock Access Time (-7.5F)  
Low Latency Operation (3:2:2 @ 133 MHz)  
The Enhanced Memory Systems SM3603 and SM3604 High-  
Speed SDRAM (HSDRAM) devices are high performance  
versions of the proposed JEDEC PC-133 SDRAM. While  
compatible with standard SDRAM, they provide the faster  
clock access time (4.6 ns), shorter random access latency  
(34.6 ns), and fast bank cycle time (52.5 ns) needed to  
improve system stability, capacity, and performance in  
systems operating at 133 MHz and higher bus speeds. The  
HSDRAM is ideal for any high performance system  
including PCs, workstations, servers, communications  
switches, DSP systems, 3-D graphics, and embedded  
computers.  
CAS Latency = 3  
RAS to CAS Delay = 2  
Precharge Delay = 2  
Fast Random Access Time (34.6 ns)  
Fast Random Cycle time (52.5 ns)  
Programmable Burst length (1, 2, 4, 8, full page)  
Programmable CAS Latency (1, 2, 3)  
Low Power suspend, Self Refresh, and Power  
Down Modes Supported  
4K Refresh / 64 ms  
Single 3.3V ± 5% Power Supply  
54-pin TSOP-II (0.8mm pin pitch)  
Block Diagram (4Mx16 shown)  
BANK A  
BANK B  
BANK C  
BANK D  
BA1  
BA0  
A(11:0)  
4K rows x  
256 col x  
16 bits  
4K rows x  
256 col x  
16 bits  
4K rows x  
256 col x  
16 bits  
4K rows x  
256 col x  
16 bits  
SENSE AMPLIFIERS  
COLUMN DECODER  
SENSE AMPLIFIERS  
COLUMN DECODER  
SENSE AMPLIFIERS  
COLUMN DECODER  
SENSE AMPLIFIERS  
COLUMN DECODER  
Data I/O Buffers  
DQ(15:0)  
CLK  
CKE  
/CS  
/RAS  
/CAS  
/WE  
COMMAND  
DECODER  
and  
TIMING  
GENERATOR  
UDQM,  
LDQM  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
1999 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Revision 1.1  
Page 1 of 10  

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