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SM320MCM42CHFNL40 PDF预览

SM320MCM42CHFNL40

更新时间： 2024-10-02 17:20:51
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路
页数 文件大小 规格书
16页 204K
描述
32-BIT, 40MHz, OTHER DSP, CQFP408, TIE-BAR, CERAMIC, QFP-408

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SM320MCM42CHFNL40 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：GQFF, TPAK408,4.0SQ,25针数：408
Reach Compliance Code：unknownECCN代码：3A991.A.2
HTS代码：8542.31.00.01风险等级：5.84
地址总线宽度：31桶式移位器：NO
位大小：32边界扫描：YES
最大时钟频率：40 MHz外部数据总线宽度：32
格式：FLOATING POINT内部总线架构：SINGLE
JESD-30 代码：S-CQFP-F408长度：67.31 mm
低功率模式：NO端子数量：408
最高工作温度：70 °C最低工作温度：
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：GQFF
封装等效代码：TPAK408,4.0SQ,25封装形状：SQUARE
封装形式：FLATPACK, GUARD RING电源：5 V
认证状态：Not QualifiedRAM（字数）：262144
座面最大高度：4.45 mm子类别：Digital Signal Processors
最大压摆率：1500 mA最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：FLAT
端子节距：0.65 mm端子位置：QUAD
宽度：67.31 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

SM320MCM42CHFNL40 数据手册

 浏览型号SM320MCM42CHFNL40的Datasheet PDF文件第2页浏览型号SM320MCM42CHFNL40的Datasheet PDF文件第3页浏览型号SM320MCM42CHFNL40的Datasheet PDF文件第4页浏览型号SM320MCM42CHFNL40的Datasheet PDF文件第5页浏览型号SM320MCM42CHFNL40的Datasheet PDF文件第6页浏览型号SM320MCM42CHFNL40的Datasheet PDF文件第7页 
SMJ320MCM42C, SMJ320MCM42D  
DUAL SMJ320C40 MULTICHIP MODULE  
SGKS001D – JULY 1997 – REVISED OCTOBER 2001  
Performance:  
‡
HFN PACKAGE  
(TOP VIEW)  
– 80 Million Floating-Point Operations Per  
Second (MFLOPS) With 496-MBps-Burst  
I/O Rate for 40-MHz Modules  
– Zero-Wait-State Local Memory for Each  
Processor  
408  
307  
1
306  
Organization:  
– 128K-Word × 32-Bit Static  
Random-Access Memory (SRAM)  
(SMJ320MCM42D)  
– 256K-Word × 32-Bit SRAM  
(SMJ320MCM42C)  
Compliant With MIL-PRF-38535 QML  
Dual C40 Performance With Local Memory  
Requiring Only 8.7 Square Inches of Board  
Space  
Enhanced Performance Offered By  
Multichip-Module Solution  
– SMJ320MCM42C  
102  
205  
– 67% Reduction in Number of  
Interconnects  
– 54% Reduction (Minimum) in Board  
Area  
103  
204  
‡
Terminal assignment information is provided by the terminal  
assignments table. Package is shown for pinout reference only.  
– Estimated 38% Reduction in Power  
Dissipation Due to Reduced Parasitic  
Capacitance and Interconnect Lengths  
– SMJ320MCM42D  
†
IEEE-1149.1 (JTAG) Boundary-Scan  
Compatible  
– 56% Reduction in Number of  
Interconnects  
– 30% Reduction (Minimum) in Board  
Area  
– Estimated 20% Reduction in Power  
Dissipation Due to Reduced Parasitic  
Capacitance and Interconnect Lengths  
408-Lead Ceramic Quad Flatpack Package  
(HFN Suffix)  
Operating Free-Air Temperature Ranges:  
–55°C to 125°C . . . (Military)  
0°C to 70°C . . . (Commercial)  
Communication-Port Connection Provided  
Between C40s for Interprocessor  
Communication  
Four Memory Ports for High Data  
Bandwidth  
– Two Full 2G-Word External Buses  
Two Internal Buses Mapped to Memory  
– 128K-Word × 32-Bit SRAM for Each C40  
Local Bus (SMJ320MCM42D)  
– 256K-Word × 32-Bit SRAM for Each C40  
Local Bus (SMJ320MCM42C)  
Ten External Communication Ports for  
Direct Processor-to-Processor  
Communication  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
IEEE Standard 1149.1–1990 Standard Test-Access Port and Boundary-Scan Architecture  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
On products compliant to MIL-STD-PRF-38535, all parameters  
are tested unless otherwise noted. On all other products,  
productionprocessingdoesnotnecessarilyincludetestingofall  
parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
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