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SM320C6424GDUQ6EP PDF预览

SM320C6424GDUQ6EP

更新时间： 2024-02-13 11:17:52
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
236页 2184K
描述
FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SM320C6424GDUQ6EP 技术参数

生命周期：Active零件包装代码：BGA
包装说明：23 X 23 MM, 1 MM PITCH, BGA-376针数：376
Reach Compliance Code：not_compliantECCN代码：3A991.A.2
HTS代码：8542.31.00.01Factory Lead Time：6 weeks
风险等级：1.52Is Samacsys：N
地址总线宽度：32桶式移位器：NO
位大小：32边界扫描：YES
最大时钟频率：30 MHz外部数据总线宽度：32
格式：FIXED POINT集成缓存：YES
内部总线架构：MULTIPLEJESD-30 代码：S-PBGA-B376
JESD-609代码：e0长度：23 mm
低功率模式：YES湿度敏感等级：3
DMA 通道数量：72端子数量：376
计时器数量：5最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA376,22X22,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：220电源：1.2,1.8,3.3 V
认证状态：Not QualifiedRAM（字数）：20480
ROM可编程性：MROM座面最大高度：2.48 mm
子类别：Digital Signal Processors最大供电电压：1.26 V
最小供电电压：1.14 V标称供电电压：1.2 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：23 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

SM320C6424GDUQ6EP 数据手册

 浏览型号SM320C6424GDUQ6EP的Datasheet PDF文件第2页浏览型号SM320C6424GDUQ6EP的Datasheet PDF文件第3页浏览型号SM320C6424GDUQ6EP的Datasheet PDF文件第4页浏览型号SM320C6424GDUQ6EP的Datasheet PDF文件第5页浏览型号SM320C6424GDUQ6EP的Datasheet PDF文件第6页浏览型号SM320C6424GDUQ6EP的Datasheet PDF文件第7页 
SM320C6424-EP  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
www.ti.com  
SPRS580–JUNE 2009  
1 Introduction  
1.1 Features  
•
High-Performance Digital Signal Processor  
(C6424)  
•
C64x+ L1/L2 Memory Architecture  
–
–
–
256K-Bit (32K-Byte) L1P Program  
RAM/Cache [Flexible Allocation]  
640K-Bit (80K-Byte) L1D Data RAM/Cache  
[Flexible Allocation]  
1M-Bit (128K-Byte) L2 Unified Mapped  
RAM/Cache [Flexible Allocation]  
–
2.5-, 2-, 1.67-, 1.43-ns Instruction Cycle  
Time  
–
400-, 500-, 600-, 700-MHz C64x+™ Clock  
Rate  
–
–
–
–
Eight 32-Bit C64x+ Instructions/Cycle  
3200, 4000, 4800, 5600 MIPS  
Fully Software-Compatible With C64x  
Commercial and Automotive (Q or S suffix)  
Grades  
•
•
Endianess: Supports Both Little Endian and  
Big Endian  
External Memory Interfaces (EMIFs)  
–
32-Bit DDR2 SDRAM Memory Controller  
With 256M-Byte Address Space (1.8-V I/O)  
–
Low-Power Device (L suffix)  
•
VelociTI.2™ Extensions to VelociTI™  
Advanced Very-Long-Instruction-Word (VLIW)  
SM320C64x+™ DSP Core  
•
Supports up to 333-MHz (data rate) bus  
and interfaces to DDR2-400 SDRAM  
–
Asynchronous 16-Bit Wide EMIF (EMIFA)  
With up to 128M-Byte Address Reach  
•
–
Eight Highly Independent Functional Units  
With VelociTI.2 Extensions:  
Flash Memory Interfaces  
•
Six ALUs (32-/40-Bit), Each Supports  
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit  
Arithmetic per Clock Cycle  
Two Multipliers Support Four 16 x 16-Bit  
Multiplies (32-Bit Results) per Clock  
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit  
Results) per Clock Cycle  
–
–
NOR (8-/16-Bit-Wide Data)  
NAND (8-/16-Bit-Wide Data)  
•
•
Enhanced Direct-Memory-Access (EDMA)  
Controller (64 Independent Channels)  
•
Two 64-Bit General-Purpose Timers (Each  
Configurable as Two 32-Bit Timers)  
–
Load-Store Architecture With Non-Aligned  
Support  
64 32-Bit General-Purpose Registers  
Instruction Packing Reduces Code Size  
All Instructions Conditional  
•
•
One 64-Bit Watch Dog Timer  
Two UARTs (One with RTS and CTS Flow  
Control)  
Master/Slave Inter-Integrated Circuit (I2C  
Bus™)  
–
–
–
–
•
•
Additional C64x+™ Enhancements  
Two Multichannel Buffered Serial Ports  
(McBSPs)  
•
•
Protected Mode Operation  
Exceptions Support for Error Detection  
and Program Redirection  
–
–
–
–
–
–
I2S and TDM  
AC97 Audio Codec Interface  
SPI  
Standard Voice Codec Interface (AIC12)  
Telecom Interfaces – ST-Bus, H-100  
128 Channel Mode  
•
Hardware Support for Modulo Loop  
Auto-Focus Module Operation  
•
C64x+ Instruction Set Features  
–
–
–
–
–
–
Byte-Addressable (8-/16-/32-/64-Bit Data)  
8-Bit Overflow Protection  
Bit-Field Extract, Set, Clear  
Normalization, Saturation, Bit-Counting  
VelociTI.2 Increased Orthogonality  
C64x+ Extensions  
•
Multichannel Audio Serial Port (McASP0)  
Four Serializers and SPDIF (DIT) Mode  
–
•
•
16-Bit Host-Port Interface (HPI)  
32-Bit 33-MHz, 3.3-V Peripheral Component  
Interconnect (PCI) Master/Slave Interface  
•
•
Compact 16-bit Instructions  
Additional Instructions to Support  
Complex Multiplies  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this document.  
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  
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