User's Guide
SLVU405–August 2010
TPS7A30-49EVM-567
This user’s guide describes the characteristics, operation, and use of theTPS7A30-49EVM-567 Evaluation
Module (EVM) as a reference design to facilitate engineering evaluation of the TPS7A3001 negative
voltage low-dropout (LDO) regulator and/or the TPS7A4901 positive voltage LDO regulator for individual
or split-rail applications. Included in this user’s guide are setup instructions, a schematic diagram, layout
and thermal guidelines, a bill of materials, and test results.
Contents
1
2
Introduction .................................................................................................................. 2
Setup ......................................................................................................................... 2
2.1
Negative Voltage Input/Output Connectors and Jumper Descriptions For TPS7A3001 LDO Circuit
........................................................................................................................ 2
Positive Voltage Input/Output Connectors and Jumper Descriptions fo the TPS7A4901 LDO
2.2
Circuit ................................................................................................................ 2
Soldering Guidelines ............................................................................................... 2
Equipment Interconnect ........................................................................................... 3
2.3
2.4
3
4
5
Operation ..................................................................................................................... 3
Adjustable Operation ....................................................................................................... 3
Test Results ................................................................................................................. 4
5.1
5.2
5.3
5.4
Turnon Output Ramp: Negative Voltage LDO, TPS7A3001 Circuit ......................................... 4
Turnon Output Ramp: Positive Voltage LDO, TPS7A4901 Circuit .......................................... 5
–VOUT Load Transient Applied to the Negative LDO Circuit, TPS7A3001 ................................ 5
+VOUT Load Transient Applied to the Positive LDO Circuit, TPS7A4901. ................................ 6
6
7
8
Thermal Guidelines ......................................................................................................... 7
Board Layout ................................................................................................................ 8
Schematic and Bill of Materials .......................................................................................... 11
8.1
8.2
Schematic ......................................................................................................... 11
Bill of Materials .................................................................................................... 12
List of Figures
1
2
3
4
5
6
7
8
9
LDO Schematic Showing the R1 and R2 Adjustment Resistors .......................................................
TPS7A3001 –VOUT Ramp at Turnon....................................................................................
TPS7A4901 +VOUT Ramp at Turnon....................................................................................
TPS7A3001 –VOUT Load Transient .....................................................................................
TPS7A4901 +VOUT Load Transient .....................................................................................
Assembly Layer .............................................................................................................
Top Layer Routing ..........................................................................................................
3
4
5
6
7
8
9
Bottom Layer Routing..................................................................................................... 10
TPS7A30-49EVM-567 Schematic....................................................................................... 11
List of Tables
1
2
Thermal Resistance, qJA, and Maximum Power Dissipation...........................................................
TPS7A30-49EVM-567 Bill of Materials ................................................................................. 12
8
PowerPAD is a trademark of Texas Instruments.
SLVU405–August 2010
1
TPS7A30-49EVM-567
Copyright © 2010, Texas Instruments Incorporated
5秒后页面跳转
MBRS340T3G手册解读：参数说明、产品特性及应用
PMOS管背靠背连接：串联还是并联？
高压电解电容的分类与选型策略
数码管：基本概念、分类、技术发展及市场趋势
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
