Datasheet > SLG46721

SLG46721

更新时间： 2023-12-20 18:45:02

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
103页	1170K
描述
GreenPAK? Programmable Mixed-signal Matrix

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SLG46721 数据手册

SLG46721

GreenPAK

Programmable Mixed Signal Array

ꢀꢀꢀꢀ

Features

Pin Configuration

•

Logic & Mixed Signal Circuits

Highly Versatile Macrocells

Read Back Protection (Read Lock)

1.8 V (±5 %) to 5 V (±10 %) Supply

Operating Temperature Range: -40 °C to 85 °C

RoHS Compliant / Halogen-Free

V_DD

GPI

GPIO

GND

20 19

20-pin STQFN: 2 x 3 x 0.55 mm, 0.4 mm pitch

GPIO

Applications

•

Personal Computers and Servers

PC Peripherals

Consumer Electronics

Data Communications Equipment

Handheld and Portable Electronics

STQFN-20

(Top View)

Block Diagram

Pin 20

GPIO

Pin 19

GPIO

Pin 18

GPIO

Pin 17

GPIO

Pin 1

Counters/Delay Generators

CNT0 CNT1 CNT4

Look Up Tables (LUTs)

Pin 16

GPIO

Pin 2

GPI

2-bit

LUT2_4

2-bit

LUT2_5

3-bit

LUT3_0

ACMP0

ACMP1

ACMP2

ACMP3

3-bit

LUT3_1

3-bit

LUT3_4

3-bit

LUT3_5

CNT5

CNT6

Pin 15

GPIO

Pin 3

GPIO

3-bit

LUT3_6

3-bit

LUT3_7

3-bit

LUT3_9

Additional Logic Functions

Pin 14

GPIO

INV_0

INV_1

Pin 4

GPIO

Combination Function Macrocells

FILTER_1

FILTER_0

2-bit

LUT2_0

or DFF4

2-bit

LUT2_1

or DFF5

2-bit

LUT2_2

or DFF6

Pin 13

GPIO

Pin 5

GPIO

2-bit

LUT2_3

or DFF7

3bit

LUT3_2

or DFF2

3-bit

LUT3_3

or DFF3

Vref

RC Oscillator

3-bit

LUT3_8 or

Pipe Delay

4-bit

LUT4_0

or CNT2

4-bit

LUT4_1

or CNT3

Pin 12

GPIO

Pin 6

GPIO

Programmable

Delay

POR

Pin 11

GND

Pin 7

GPIO

Pin 8

GPIO

Pin 9

GPIO

Pin 10

GPIO

Revision 1.22

Revised August 15, 2023

12 3 4 5 6 7...103

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