Datasheet > SL23EP09

SL23EP09

更新时间： 2024-01-01 07:29:12

品牌	Logo	应用领域
SPECTRALINEAR		/
页数	文件大小	规格书
13页	157K
描述
Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)

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SL23EP09 数据手册

SL23EP09

Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)

Key Features

Description

10 to 220 MHz operating frequency range

Low output clock skew: 45ps-typ

Low output clock jitter:

The SL23EP09 is a low skew, low jitter and low power Zero

Delay Buffer (ZDB) designed to produce up to nine (9) clock

outputs from one (1) reference input clock, for high speed

clock distribution applications.

25 ps-typ cycle-to-cycle jitter

15 ps-typ period jitter

The product has an on-chip PLL which locks to the input

clock at CLKIN and receives its feedback internally from the

CLKOUT pin.

Low part-to-part output skew: 90 ps-typ

Wide 2.5 V to 3.3 V power supply range

Low power dissipation:

The SL23EP09 has two (2) clock driver banks each with four

(4) clock outputs. These outputs are controlled by two (2)

select input pins S1 and S2. When only four (4) outputs are

needed, four (4) bank-B output clock buffers can be tri-stated

to reduce power dissipation and jitter. The select inputs can

also be used to tri-state both banks A and B or drive them

directly from the input bypassing the PLL and making the

product behave like a Non-Zero Delay Buffer (NZDB).

26 mA-max at 66 MHz and VDD=3.3 V

24 mA-max at 66 MHz and VDD=2.5V

One input drives 9 outputs organized as 4+4+1

Select mode to bypass PLL or tri-state outputs

SpreadThru™ PLL that allows use of SSCG

Standard and High-Drive options

The high-drive version operates up to 220MHz and 200MHz

at 3.3V and 2.5V power supplies respectively.

Available in 16-pin SOIC and TSSOP packages

Available in Commercial and Industrial grades

Benefits

Applications

Up to nine (9) distribution of input clock

Printers, MFPs and Digital Copiers

Standard and High-Dirive levels to control impedance

level, frequency range and EMI

PCs and Work Stations

Routers, Switchers and Servers

Digital Embeded Systems

Low power dissipation, jitter and skew

Low cost

Block Diagram

Low Power and

Low Jitter

PLL

MUX

CLKOUT

CLKIN

CLKA1

CLKA2

CLKA3

CLKA4

Input Selection

Decoding Logic

CLKB1

CLKB2

CLKB3

CLKB4

VDD

GND

Rev 1.1, February 2, 2007

Page 1 of 13

2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com

12 3 4 5 6 7...13

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与SL23EP09相关器件

型号	品牌	获取价格	描述	数据表
SL23EP09NZ	SPECTRALINEAR	获取价格	Low Jitter and Skew DC to 220MHz Clock Buffer
SL23EP09NZ	SILICON	获取价格	Low Jitter and Skew DC to 220 MHz Clock Buffer
SL23EP09NZSC-1H	SILICON	获取价格	Low Skew Clock Driver, 23EP Series, 9 True Output(s), 0 Inverted Output(s), PDSO16, SOIC-1
SL23EP09NZSC-1HT	SILICON	获取价格	Low Jitter and Skew DC to 220 MHz Clock Buffer
SL23EP09NZSI-1H	SILICON	获取价格	Low Jitter and Skew DC to 220 MHz Clock Buffer
SL23EP09NZSI-1HT	SILICON	获取价格	Low Jitter and Skew DC to 220 MHz Clock Buffer
SL23EP09SC-1	SPECTRALINEAR	获取价格	Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)
SL23EP09SC-1H	SPECTRALINEAR	获取价格	Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)
SL23EP09SC-1HT	SPECTRALINEAR	获取价格	Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)
SL23EP09SC-1T	SPECTRALINEAR	获取价格	Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)

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