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SL23EP08ZI-1HT

更新时间： 2024-02-03 21:55:27
品牌 Logo 应用领域
SPECTRALINEAR 逻辑集成电路光电二极管驱动
页数 文件大小 规格书
18页 174K
描述
Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)

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SL23EP08ZI-1HT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.63其他特性：ALSO OPERATES WITH 3.3V SUPPLY
系列：23EP输入调节：MUX
JESD-30 代码：R-PDSO-G16长度：4.4 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER功能数量：2
反相输出次数：端子数量：16
实输出次数：4最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.5 ns座面最大高度：1.1 mm
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3 mm
最小 fmax：220 MHzBase Number Matches：1

SL23EP08ZI-1HT 数据手册

 浏览型号SL23EP08ZI-1HT的Datasheet PDF文件第2页浏览型号SL23EP08ZI-1HT的Datasheet PDF文件第3页浏览型号SL23EP08ZI-1HT的Datasheet PDF文件第4页浏览型号SL23EP08ZI-1HT的Datasheet PDF文件第5页浏览型号SL23EP08ZI-1HT的Datasheet PDF文件第6页浏览型号SL23EP08ZI-1HT的Datasheet PDF文件第7页 
Preliminary  
SL23EP08  
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)  
Key Features  
Description  
The SL23EP08 is a low skew, low jitter and low power  
Zero Delay Buffer (ZDB) designed to produce up to eight  
(8) clock outputs from one (1) reference input clock, for  
high speed clock distribution applications.  
x
x
x
10 to 220 MHz operating frequency range  
Low output clock skew: 70ps-typ  
Low output clock Jitter: 50 ps-typ  
- 50 ps-typ at 166MHz, CL=15pF and VDD=3.3V  
- 75 ps-typ at 166MHz, CL=15pF and VDD=2.5V  
Low part-to-part output skew: 150 ps-typ  
3.3V to 2.5V power supply range  
The product has an on-chip PLL and a feedback pin (FBK)  
which can be used to obtain feedback from any one of the  
output clocks. The SL23EP08 has two (2) clock driver  
banks each with four (4) clock outputs. These outputs are  
controlled by two (2) select input pins S1 and S2. When  
only four (4) outputs are needed, bank-B output clock  
buffers can be tri-stated to reduce power dissipation and  
jitter. The select inputs can also be used to tri-state both  
banks A and B or drive them directly from the input  
bypassing the PLL and making the product behave like a  
Non-Zero Delay Buffer (NZDB). The SL23EP08 offers  
various X/2,1X, 2X and 4x frequency options at the output  
clocks. Refer to the “Product Configuration Table” for the  
details.  
x
x
x
Low power dissipation:  
x
x
- 22 mA-typ at 66MHz and VDD=3.3V  
- 20 mA-typ at 66MHz and VDD=2.5V  
One input drives 8 outputs  
x
x
x
x
x
x
Multiple configurations and drive options  
Select mode to bypass PLL or tri-state outputs  
SpreadThru™ PLL that allows use of SSCG  
Available in 16-pin SOIC and TSSOP packages  
Available in Commercial and Industrial grades  
The SL23EP08-1H, -2H and 5H versions operates up to  
220 MHz and SL23EP08-1, -2, -3 and -4 versions operate  
up to 133 MHz with CL=15pF output load.  
Applications  
Benefits  
x
x
x
x
x
Printers, MFPs and Digital Copiers  
PCs and Work Stations  
x
x
Up to eight (8) distribution of input clock  
Routers, Switchers and Servers  
Datacom and Telecom  
Standard and High-Dirive levels to control  
impedance level, frequency range and EMI  
x
Low skew, jitter and power dissipation  
High-Speed Digital Embeded Systems  
Block Diagram  
/2  
Low Power and  
Low Jitter  
PLL  
(Divider for -3 and -4)  
CLKIN  
/2  
MUX  
FBK  
(Divider for -5H only)  
CLKA1  
CLKA2  
CLKA3  
CLKA4  
S2  
S1  
Input Selection  
Decoding Logic  
/2  
(Divider for -2, -2H and -3)  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
2
2
VDD  
GND  
Rev 1.4, May 28, 2007  
Page 1 of 18  
2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com  
1234567...18

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