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SK1802WDT PDF预览

SK1802WDT

更新时间: 2024-02-28 14:28:06
品牌 Logo 应用领域
商升特 - SEMTECH 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
6页 73K
描述
Clock Generator, 622.08MHz, CMOS, PDSO16, SOIC-16

SK1802WDT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.91
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:10.21 mm端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:622.08 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
主时钟/晶体标称频率:77.76 MHz认证状态:Not Qualified
座面最大高度:2.64 mm最大供电电压:5.5 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

SK1802WDT 数据手册

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SK1802W  
SONET OC-12  
Clock Synthesizer  
ADVANCED  
Features  
Description  
The SK1802W phase locked loop is a SONET compliant  
clock generator providing 622.08 MHz for OC-12 /  
STS-12 applications. It can accept either a TTL input  
reference clock (51.84 MHz or 77.76 MHz) or a quartz  
crystal.  
• Extended Supply Voltage Range: (VCC =+3.0V  
to +5.5V, VEE = 0V)  
• High Bandwidth Output Transition  
• Differential 622.08 MHz PECL Outputs  
• SONET compliant jitter performance (- 0.01 UI)  
• Choice of Reference Clock or a Quartz Crystal  
Frequencies  
• Complies with Bellcore, CCITT, and ANSI Standards  
• Fully Compatible with Industry Standard 10KH  
I/O Levels  
SEL_52/78 input (TTL) allows users to choose between  
a TTL clock 51.84 MHz or 77.76 MHz, the default for  
this input is set to 77.76 MHz. The REFCLK_SEL  
input (TTL) selects between the DIN  
and XTAL1  
TTL  
and XTAL2. The default settings for REFCLK_SEL input  
are XTAL1 and XTAL2. The differential PECL outputs  
meet the Bellcore and ANSI Standards.  
• ESD Protection >4000V  
• Available in 16 pin Wide-Body SOIC Package  
The test input allows the user to measure the VOH  
and VOL DC parameters. To make these measurements  
the test input must be set to a logic high.  
Functional Block Diagram  
RC  
DIN  
0
1
TTL  
622 MHz  
VCO  
Charge Pump  
PFD  
XTAL1  
OSC  
XTAL2  
1
Q_622  
PECL  
REFCLK_SEL  
Feed Back  
¸ 2 / 3  
¸ 4  
Q*_622  
0
SEL_52/78  
(TTL)  
VCC  
VCCO  
GND  
TEST  
VCCA  
Revision 1/August 27, 2001  
www.semtech.com  
1

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