SK12430
High ꢀrequency Clock Synthesizer
HIGH-PERꢀORMANCE PRODUCTS
ADVANCED
Description
The SK12430 is a general purpose synthesized clock
source. Its internal VCO will operate over a range of
frequencies from 400 to 800MHz. The differential
PECL output can be configured to be the VCO frequency
divided by 1, 2, 4 or 8. With the output configured to
divide the VCO frequency by 2, and with a 16.000MHz
external quartz crystal used to provide the reference
frequency, the output frequency can be specified in
1MHz steps. The PLL loop filter is fully integrated so
that no external components are required. The syn-
thesizer output frequency is configured using a paral-
lel or serial interface.
internal logic is separated from the power supply for
the phase-locked loop to minimize noise induced jitter.
The configuration logic has two sections: serial and
parallel. The parallel interface uses the values at the
M[8:0] and N[1:0] inputs to configure the internal
counters. Normally, on system reset, the P_LOAD in-
put is held LOW until sometime after power becomes
valid.. On the LOW -to-HIGH transition of P_LOAD, the
parallel inputs are captured. The parallel interface
has priority over the serial interface. Internal pullup
resistors are provided on the M[8:0] and N[1:0] in-
puts to reduce component count in the application of
the chip.
The internal oscillator uses the external quartz crystal
as the basis of its frequency reference. The output of
the reference oscillator is divided by 16 before being
sent to the phase detector. With a 16MHz crystal,
this provides a reference frequency of 1MHz. Although
this data sheet illustrates functionality only for a 16MHz
crystal, any crystal in the 10-20MHz range can be used.
The serial interface centers on a fourteen bit shift
register. The shift register shifts once per rising edge
of the S_Clock input. The configuration logic has two
sections: serial and parallel. The parallel interface
uses the values at the M[8:0] and N[1:0] inputs to
configure the internal counters. Normally, on system
reset, the P_LOAD input is held LOW until sometime
after power becomes valid.. On the LOW -to-HIGH tran-
sition of P_LOAD, the parallel inputs are captured. The
parallel interface has priority over the serial interface.
Internal pullup resistors are provided on the M[8:0]
and N[1:0] inputs to reduce component count in the
application of the chip.
The VCO within the PLL operates over a range of 400
to 800 MHz. Its output is scaled by a divider that is
configured by either the serial or parallel interfaces.
The output of this loop divider is applied to the phase
detector.
The phase detector and loop filter attempt to force
the VCO output frequency to be M X 2 times the refer-
ence frequency by adjusting the VCO control voltage.
Note that for some values of M (either too high or too
low) the PLL will not achieve loop lock. (N divider) is
configured through either the serial of the parallel in-
terfaces and can provide one of four division ratios
(1, 2, 4 or 8). This divider extends performance of
the part while providing a 50% duty cycle.
The TEST output reflects various internal node values,
and is controlled by the T[2:0] bits in the serial data
stream. See the programming section for more infor-
mation.
ꢀeatures
• 50 to 800MHz Differential PECL Outputs
• +25ps Peak-to-Peak Outputs
• Fully Integrated Phase-Locked Loop
• Minimal Frequency Over-Shoot
• Serial 3-Wire Interface
The output driver is driven differentially from the out-
put divider and is capable of driving a pair of trans-
mission lines terminated in 50Ω to VCC - 2.0V. The
positive reference for the output driver and the
• Parallel Interface for Power-Up
• Quartz Crystal Interface
• 28-Lead PLCC Package
• Operates from 3.3V or 5.0V Power Supply
• ESD Protection of >4000V
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Revision 1/ꢀebruary 8, 2001
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