Datasheet > SK12429D

SK12429D

更新时间： 2023-12-18 00:00:00

品牌	Logo	应用领域
商升特 - SEMTECH		光电二极管外围集成电路
页数	文件大小	规格书
14页	167K
描述
Clock Generator, CMOS, PDSO28, SOIC-28

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SK12429D 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.83
JESD-30 代码：	R-PDSO-G28	长度：	17.9 mm
端子数量：	28	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
座面最大高度：	2.65 mm	表面贴装：	YES
技术：	CMOS	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	7.5 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

SK12429D 数据手册

SK12429

High Frequency PLL

Frequency Synthesizer

ADVANCED

HIGH-PERFORMANCE PRODUCTS

Description

The SK12429 is a general purpose synthesized clock

source targeting applications that require both serial

and parallel interfaces. Its internal VCO will operate

over a range of frequencies from 400 to 800 MHz.

The differential PECL output can be configured to be

the VCO frequency divided by 2, 4, 8, or 16. With the

output configured to divide the VCO frequency by 2,

and with a 16.000 MHz external quartz crystal used

to provide the reference frequency, the output frequency

can be specified in 1 MHz steps. The PLL loop filter

is fully integrated so that no external components are

required.

The configuration logic has two sections: serial and

parallel. The parallel interface uses the values at the

M[8:0] and N[1:0] inputs to configure the internal

counters. Normally, on system reset, the P_LOAD*

input is held LOW until sometime after power becomes

valid. On the LOW-to-HIGH transition of P_LOAD*, the

parallel inputs are captured. The parallel interface

has priority over the serial interface. Internal pull-up

resistors are provided on the M[8:0] and N[1:0] inputs

to reduce component count in the application of the

chip.

The serial interface centers on a 14-bit shift register.

The shift register shifts once per rising edge of the

S_CLOCK input. The serial input S_DATA must meet

setup and hold time as specified in the AC

Characteristics section of this document. The

configuration latches will capture the value of the shift

See the programming section for more information.

The internal oscillator uses the external quartz crystal

as the basis of its frequency reference. The output of

the reference oscillator is divided by 8 before being

sent to the phase detector. With a 16 MHz crystal,

this provides a reference frequency of 2 MHz. Although

this datasheet illustrates functionality only for a 16

MHz crystal, any crystal in the 10 -20 MHz range can be

used.

The TEST output reflects various internal node values,

and is controlled by the T[2:0] bits in the serial data

stream. See the programming section for more

information.

The VCO within the PLL operates over a range of 400

to 800 MHz. Its output is scaled by a divider that is

configured by either the serial or parallel interface.

The output of this loop divider is also applied to the

phase detector.

Features

The phase detector and loop filter attempt to force

the VCO output frequency to be M times the reference

frequency by adjusting the VCO control voltage. Note

that for some values of M (either too high or too low)

the PLL will not achieve loop lock.

• Operates from 3.0V to 5.5V Power Supply

• 25 to 400 MHz Differential PECL Outputs

•

25 ps Peak-to-Peak Output Jitter

• Fully Integrated Phase-Locked Loop

• Minimal Frequency Over-Shoot

• Synthesized Architecture

• Serial 3-Wire Interface

• Parallel Interface for Power-Up

• Quartz Crystal Interface

• Available in 28-Lead PLCC Package

• ESD Protection of >4000V

• Industrial Temperature Range: 0^oC to 70^oC

• flammability

The output of the VCO is also passed through an output

divider before being sent to the PECL output driver.

This output divider (N divider) is configured through

either the serial or the parallel interfaces, and can

provide one of four division ratios (2, 4, 8, or 16).

This divider extends performance of the part while

providing a 50% duty cycle.

The output driver is driven differentially from the output

divider, and is capable of driving a pair of transmission

• moisture sensitivity

lines terminated in 50W to V

– 2.0V. The positive

reference for the output driver and the internal logic

is separated from the power supply for the phase-

locked loop to minimize noise induced jitter.

www.semtech.com

Revision 1/January 9, 2002

12 3 4 5 6 7...14

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与SK12429D相关器件

型号	品牌	获取价格	描述	数据表
SK12429LVPJ	SEMTECH	获取价格	Clock Generator, 400MHz, CMOS, PQCC28, PLASTIC, LCC-28
SK12429PJ	SEMTECH	获取价格	Clock Generator, 400MHz, CMOS, PQCC28, PLASTIC, LCC-28
SK12430PJ	SEMTECH	获取价格	Clock Generator, 800MHz, CMOS, PQCC28, PLASTIC, LCC-28
SK12430PJT	SEMTECH	获取价格	Clock Generator, 800MHz, CMOS, PQCC28, PLASTIC, LCC-28
SK1250C	DEC	获取价格	12 AMP SCHOTTKY BARRIER RECTIFIERS
SK1260C	DEC	获取价格	12 AMP SCHOTTKY BARRIER RECTIFIERS
SK1270C	DEC	获取价格	12 AMP SCHOTTKY BARRIER RECTIFIERS
SK1288	UTC	获取价格	2-PHASE DC-FAN MOTOR DRIVER
SK1288_15	UTC	获取价格	2-PHASE DC-FAN MOTOR DRIVER
SK1288L-S08-R	UTC	获取价格	2-PHASE DC-FAN MOTOR DRIVER

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