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SK10E116

更新时间： 2024-09-15 22:43:11

品牌	Logo	应用领域
商升特 - SEMTECH		/
页数	文件大小	规格书
4页	113K
描述
Quint Differential Line Receiver

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数据手册

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SK10E116 数据手册

SK10/100E116

Quint Differential

Line Receiver

HIGH-PERꢀORMANCE PRODUCTS

ꢀeatures

Description

The SK10/100E116 is a quint differential line receiver

designed for use in new, high-performance ECL systems.

•

500 ps Maximum Propagation Delay

Extended VEE Range of –4.2V to –5.5V

VBB Output for Single-Ended Reception

Internal 75KΩ Input Pull-Down Resistors

ESD Protection of >4000V

Fully Compatible with MC10E/100E116

Specified Over Industrial Temperature Range:

–40^oC to +85^oC

The receiver design features clamp circuitry to cause a

defined output state if both the inverting and non-inverting

inputs are left open; in this case the Q output goes low,

while the Q* output goes high. This feature makes the

device ideal for twisted pair applications.

•

Available in 28-Pin PLCC Package

If both inverting and non-inverting inputs are at an equal

potential of >–2.9V, the receiver does not go to a defined

state, but rather shares current in normal differential

amplifier fashion, producing output voltage levels midway

between high and low. This may even cause the device to

oscillate.

PIN Description

The SK10/100E116 provides VBB output for either single-

ended use or as a DC bias for AC coupling to the device.

The VBB output pin should be used only as a DC bias for

the E116 as its current sink/source capability is limited.

Whenever used, the VBB pin should be bypassed to VCC

via a 0.01 µF capacitor.

D0, D0*D4, D4*

Q0, Q0*-Q4, Q4*

VBB

ꢀunction

Differential Input Pairs

Differential Output Pairs

Reference Voltage Output

VCC to Output

VCC0

ꢀunctional Block Diagram

D0*

Q0*

D1*

Q1*

D3*

Q3*

D2*

VEE

VBB

VCC

Q2*

D2*

Q2*

PLCC

TOPVIEW

VCC0

Q1*

D3*

Q3*

D0*

D4*

Q4*

VBB

www.semtech.com

Revision 1 /ꢀebruary 21, 2001

12 3 4

中文翻译

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