SK10E111

更新时间： 2024-09-15 22:43:11

品牌	Logo	应用领域
商升特 - SEMTECH		时钟驱动器
页数	文件大小	规格书
6页	155K
描述
1:9 Differential Clock Driver

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数据手册

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SK10E111 数据手册

SK10/100E111

1:9 Differential

Clock Driver

HIGH-PERꢀORMANCE PRODUCTS

PRELIMINARY

ꢀeatures

Description

• Low Skew

• Guaranteed Skew Spec

• Differential Design

The SK10E/100E111 is a low skew 1-to-9 differential

driver designed with clock distribution in mind. It accepts

one signal input which can be either differential or single-

ended if the VBB output is used. The signal is fanned

out to 9 identical differential outputs. An enable input

is also provided. A HIGH disables the device by forcing

all Q outputs LOW and all Q* outputs HIGH.

• V Output

• Enable Input

• Extended 100E V Range of –4.2 to –5.5V

• 75KΩ Internal Input Pulldown Resistors

• Fully Compatible with MC10E111 and

MC100E111

The device is specifically designed, modeled, and

produced with low skew as the key goal. Optimal design

and layout serve to minimize gate-to-gate skew within-

device,and characterization is used to determine process

control limits that ensure consistent tpd distributions

from lot to lot. The net result is a dependable, guaranteed

low skew device.

• Specified Over Industrial Temperature Range:

–40^oC to 85^oC

• ESD Protection of >4000V

• Available in 28-pin PLCC Package

ꢀunctional Block Diagram

To ensure that the tight skew specification is met, it is

necessary that both sides of the differential output are

terminated into 50Ω,even if only one side is being used.

In most applications, all nine differential pairs will be

used and therefore terminated. In the case where fewer

than nine pairs are used, it is necessary to terminate at

least the output pairs on the same package side (i.e.

Q0*

Q1*

sharing the same V

) as the pair(s) being used on

CCO

that side in order to maintain minimum skew. Failure to

do this will result in small degradations of propagation

delay (on the order of 10–20ps) of the output(s) being

used which, while not being catastrophic to most designs,

will mean a loss of skew margin.

Q2*

Q3*

Q4*

IN*

Q5*

EN*

Q6*

Q7*

Q8*

www.semtech.com

Revision 1 /ꢀebruary 13, 2001

12 3 4 5 6

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