Datasheet > SigmaQuad-II+ (B2)

SigmaQuad-II+ (B2)

更新时间： 2024-11-22 14:57:11

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GSI		/
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23页	397K
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BGA Package

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数据手册

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GS82582QT19/37RE-350M/250M

GS81302QT19/37RE-350M/250M

GS8662QT19/37RE-350M/250M

350 MHz–250 MHz

1.8 V V_DD

1.8 V and 1.5 V I/O

Rad-Tolerant SRAM

288Mb/144Mb/72Mb Burst of 2 SigmaQuad-II+^TM

165-Bump BGA

Military Temp

Features

SigmaQuad™ Family Overview

• Aerospace-Level Product

The GS82582QT19/37, GS81302QT19/37, and

• 2.0 clock Latency

GS8662QT19/37 are built in compliance with the

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Dual-Range On-Die Termination (ODT) on Data (D), Byte

Write (BW), and Clock (K, K) inputs

• Burst of 2 Read and Write

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 301,989,888-bit (288Mb),

150,994,944-bit (144Mb), and 75,497,472-bit (72Mb) SRAMs.

These SigmaQuad SRAMs comprise a family of low power,

low voltage HSTL I/O Radiation-Tolerant (Rad-Tolerant)

SRAMs designed to operate in Radiation environments.

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

Clocking and Addressing Schemes

The Rad-Tolerant SigmaQuad-II+ SRAMs are synchronous

devices. They employ two input register clock inputs, K and K.

K and K are independent single-ended clock inputs, not

differential inputs to a single differential clock input buffer.

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump leaded BGA package

Each internal read and write operation in a SigmaQuad-II+ B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore, the address field of a

SigmaQuad-II+ B2 RAM is always one address pin less than

the advertised index depth (e.g., the 8M x 36 has an 4M

addressable index).

Radiation Performance

• Total Ionizing Dose (TID) > 50krads(Si)

• Destructive Single Event Latchup Immunity >42.2 MeV.cm²/mg

(100C)

Parameter Synopsis

-350M

2.86 ns

0.45 ns

-250M

4.0 ns

0.45 ns

tKHKH

tKHQV

Rev: 1.01a 9/2020

1/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...23

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