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SI5368A-B-GQ

更新时间: 2024-09-17 04:04:43
品牌 Logo 应用领域
芯科 - SILICON ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路衰减器异步传输模式时钟
页数 文件大小 规格书
18页 714K
描述
ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

SI5368A-B-GQ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:HTFQFP,针数:100
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.78Is Samacsys:N
应用程序:SONET;SDHJESD-30 代码:S-PQFP-G100
长度:16 mm功能数量:1
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HTFQFP封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.2 mm
标称供电电压:1.8 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:16 mmBase Number Matches:1

SI5368A-B-GQ 数据手册

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Si5368  
PRELIMINARY DATA SHEET  
ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR  
Description  
Features  
The Si5368 is a jitter-attenuating precision clock multiplier for  
applications requiring sub 1 ps rms jitter performance. The  
Si5368 accepts four clock inputs ranging from 2 kHz to  
710 MHz and generates five independent, synchronous clock  
outputs ranging from 2 kHz to 945 MHz and select  
frequencies to 1.4 GHz. The device provides virtually any  
frequency translation combination across this operating  
range. The outputs are divided down separately from a  
common source. The Si5368 input clock frequency and clock  
multiplication ratio are programmable through an I2C or SPI  
interface. The Si5368 is based on Silicon Laboratories' 3rd-  
generation DSPLL® technology, which provides any-rate  
frequency synthesis and jitter attenuation in a highly  
integrated PLL solution that eliminates the need for external  
VCXO and loop filter components. The DSPLL loop  
bandwidth is digitally programmable, providing jitter  
performance optimization at the application level. Operating  
from a single 1.8 or 2.5 V supply, the Si5368 is ideal for  
providing clock multiplication and jitter attenuation in high  
performance timing applications.  
Generates any frequency from 2 kHz to 945 MHz  
and select frequencies to 1.4 GHz from an input  
frequency of 2 kHz to 710 MHz  
Ultra-low jitter clock outputs w/jitter generation as  
low as 0.3 ps rms (50 kHz–80 MHz)  
Integrated loop filter with selectable loop bandwidth  
(60 Hz to 8.4 kHz)  
Meets OC-192 GR-253-CORE jitter specifications  
Four clock inputs w/manual or automatically  
controlled hitless switching  
Five clock outputs with selectable signal format  
(LVPECL, LVDS, CML, CMOS)  
SONET frame sync switching and regeneration  
Support for ITU G.709 and custom FEC ratios  
(255/238, 255/237, 255/236)  
LOL, LOS, FOS alarm outputs  
Digitally-controlled output phase adjust  
Applications  
2
I C or SPI programmable settings  
SONET/SDH OC-48/OC-192 line cards  
GbE/10GbE, 1/2/4/8/10GFC line cards  
ITU G.709 and custom FEC line cards  
Wireless basestations  
Data converter clocking  
xDSL  
On-chip voltage regulator for 1.8 or 2.5 V ±10%  
operation  
Small size: 14 x 14 mm 100-pin TQFP  
Pb-free, RoHS compliant  
SONET/SDH + PDH clock synthesis  
Test and measurement  
Xtal or Refclock  
CKIN1  
CKIN2  
÷ N31  
÷ N32  
÷ N33  
÷ N34  
÷ NC1  
÷ NC2  
CKOUT1  
CKOUT2  
®
DSPLL  
CKIN3  
CKIN4  
÷ N2  
÷ NC3  
÷ NC4  
÷ NFS  
CKOUT3  
I2C/SPI Port  
Rate Select  
CKOUT4  
Clock Select  
Latency Control  
FSYNC Realignment  
Device Interrupt  
LOL/LOS/FOS Alarms  
Control  
Output Clock 2  
CKOUT5/FS_OUT  
VDD (1.8 or 2.5 V)  
GND  
Input Clock 3  
Input Clock 4  
Preliminary Rev. 0.3 3/07  
Copyright © 2007 by Silicon Laboratories  
Si5368  
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.  

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