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SI5367C-C-GQ PDF预览

SI5367C-C-GQ

更新时间: 2024-11-07 19:32:11
品牌 Logo 应用领域
芯科 - SILICON ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
80页 310K
描述
Support Circuit, 1-Func, PQFP100, TQFP-100

SI5367C-C-GQ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:HTFQFP,针数:100
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.79应用程序:SONET;SDH
JESD-30 代码:S-PQFP-G100长度:14 mm
功能数量:1端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HTFQFP
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.2 mm标称供电电压:1.8 V
表面贴装:YES电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

SI5367C-C-GQ 数据手册

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Si5367  
µP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER  
Features  
Not recommended for new  
designs. For alternatives, see the  
Si533x family of products.  
Five clock outputs with selectable  
signal format (LVPECL, LVDS,  
CML, CMOS)  
Generates any frequency from Support for ITU G.709 FEC ratios  
2 kHz to 945 MHz and select  
frequencies to 1.4 GHz from an  
input frequency of 10 to 710 MHz  
(255/238, 255/237, 255/236)  
LOS alarm outputs  
2
I C or SPI programmable  
Low jitter clock outputs w/jitter  
generation as low as 0.6 ps rms  
(50 kHz–80 MHz)  
settings  
On-chip voltage regulator for  
1.8 V ±5%, 2.5 V ±10%, or  
3.5 V ±10% operation  
Ordering Information:  
Integrated loop filter with  
selectable loop bandwidth  
(150 kHz to 1.3 MHz)  
See page 73.  
Small size: 14 x 14 mm 100-pin  
TQFP  
Four clock inputs with manual or  
automatically controlled  
switching  
Pb-free, RoHS compliant  
Applications  
SONET/SDH OC-48/OC-192 STM-  
16/STM-64 line cards  
GbE/10GbE, 1/2/4/8/10GFC line  
cards  
ITU G.709 and custom FEC line  
cards  
Wireless base stations  
Data converter clocking  
xDSL  
SONET/SDH + PDH clock synthesis  
Test and measurement  
Description  
The Si5367 is a low jitter, precision clock multiplier for applications requiring clock  
multiplication without jitter attenuation. The Si5367 accepts four clock inputs  
ranging from 10 to 707 MHz and generates five frequency-multiplied clock outputs  
ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device  
provides virtually any frequency translation combination across this operating  
range. The outputs are divided down separately from a common source. The  
Si5367 input clock frequency and clock multiplication ratio are programmable  
through an I2C or SPI interface. The Si5367 is based on Silicon Laboratories' 3rd-  
generation DSPLL® technology, which provides any-frequency synthesis in a  
highly integrated PLL solution that eliminates the need for external VCXO and  
loop filter components. The DSPLL loop bandwidth is digitally programmable,  
providing jitter performance optimization at the application level. Operating from a  
single 1.8, 2.5, or 3.5 V supply, the Si5367 is ideal for providing clock  
multiplication in high performance timing applications.  
Rev. 0.5 2/12  
Copyright © 2012 by Silicon Laboratories  
Si5367  

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