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SI5366-RM PDF预览

SI5366-RM

更新时间: 2024-09-17 21:21:23
品牌 Logo 应用领域
芯科 - SILICON ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
32页 569K
描述
Mux/Demux, 1-Func, PQFP100, TQFP-100

SI5366-RM 技术参数

生命周期:Active零件包装代码:QFP
包装说明:QFP,针数:100
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.8JESD-30 代码:S-PQFP-G100
功能数量:1端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
标称供电电压:1.8 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH MUX/DEMUX温度等级:INDUSTRIAL
端子形式:GULL WING端子位置:QUAD
Base Number Matches:1

SI5366-RM 数据手册

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Si5366  
PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR  
Features  
Selectable output frequencies  
SONET frame sync switching  
ranging from 8 kHz to 1050 MHz  
and regeneration  
Ultra-low jitter clock outputs  
w/jitter generation as low as  
0.3 ps rms (12 kHz–20 MHz)  
Support for ITU G.709 FEC ratios  
(255/238, 255/237, 255/236)  
LOL, LOS, FOS alarm outputs  
Integrated loop filter with  
selectable loop bandwidth (60 Hz  
to 8.4 kHz)  
Pin-controlled output phase  
adjust  
Pin-programmable settings  
Meets OC-192 GR-253-CORE  
On-chip voltage regulator for  
1.8 ±5%, 2.5 V ±10%, or  
3.3 V ±10% operation  
jitter specifications  
Ordering Information:  
Four clock inputs w/manual or  
automatically controlled hitless  
switching  
See page 25.  
Small size: 14 x 14 mm 100-pin  
TQFP  
Five clock outputs with selectable  
signal format (LVPECL, LVDS,  
CML, CMOS)  
Pb-free, RoHS-compliant  
Applications  
SONET/SDH OC-48/STM-16  
Optical modules  
and OC-192/STM-64 line cards  
Test and measurement  
Synchronous Ethernet  
GbE/10GbE, 1/2/4/8/10G Fibre  
Channel line cards  
ITU G.709 line cards  
Description  
The Si5366 is a jitter-attenuating precision clock multiplier for high-speed  
communication systems, including SONET OC-48/OC-192, Ethernet, and  
Fibre Channel. The Si5366 accepts four clock inputs ranging from 8 kHz  
to 707 MHz and generates five frequency-multiplied clock outputs ranging  
from 8 kHz to 1050 MHz. The input clock frequency and clock  
multiplication ratio are selectable from a table of popular SONET,  
Ethernet, and Fibre Channel frequencies. The Si5366 is based on Silicon  
®
Laboratories' 3rd-generation DSPLL technology, which provides any-  
frequency synthesis and jitter attenuation in a highly integrated PLL  
solution that eliminates the need for external VCXO and loop filter  
components. The DSPLL loop bandwidth is digitally programmable,  
providing jitter performance optimization at the application level.  
Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5366 is ideal for  
providing clock multiplication and jitter attenuation in high performance  
timing applications.  
Rev. 1.0 8/12  
Copyright © 2012 by Silicon Laboratories  
Si5366  

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