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SI53152-A01AGM PDF预览

SI53152-A01AGM

更新时间： 2024-09-16 14:23:11
品牌 Logo 应用领域
芯科 - SILICON 驱动逻辑集成电路
页数 文件大小 规格书
22页 393K
描述
Low Skew Clock Driver, 53152 Series, 4 True Output(s), 0 Inverted Output(s), QFN-24

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中文翻译

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SI53152-A01AGM 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：QFN包装说明：HVQCCN, LCC24,.16SQ,20
针数：24Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：1.69
系列：53152输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-XQCC-N24长度：4 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER最大I（ol）：0.001 A
功能数量：1反相输出次数：
端子数量：24实输出次数：4
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC24,.16SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE电源：3.3 V
认证状态：Not Qualified座面最大高度：0.8 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD宽度：4 mm
Base Number Matches：1

SI53152-A01AGM 数据手册

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Si53152  
PCI-EXPRESS  
G
EN 1, GEN 2, GEN 3, AND  
G
EN  
4
F
ANOUT  
B
UFFER  
Features  
PCI-Express Gen 1, Gen 2, Gen 3, Dedicated output enable pin for  
and Gen 4 common clock  
compliant  
Supports Serial ATA (SATA) at  
100 MHz  
100–210 MHz operation  
Low power, push pull, differential  
output buffers  
Internal termination for maximum  
integration  
each clock  
Two PCI-Express buffered clock  
outputs  
Supports LVDS outputs  
I2C support with readback  
capabilities  
Extended temperature:  
–40 to 85 °C  
3.3 V Power supply  
24-pin QFN package  
Ordering Information:  
See page 17  
Applications  
Network attached storage  
Multi-function Printer  
Wireless access point  
Routers  
Pin Assignments  
Description  
24  
23  
22  
21  
20  
19  
OE_DIFF1*  
VDD  
18  
17  
16  
15  
VDD  
1
2
3
4
5
6
The Si53152 is a spread spectrum tolerant PCIe clock buffer that can source  
two PCIe clocks simultaneously. The device has two hardware output enable  
inputs for enabling the respective differential outputs on the fly. The device  
also features output enable control through I2C communication. I2C  
programmability is also available to dynamically control skew, edge rate and  
amplitude on the true, compliment, or both differential signals on the clock  
outputs. This control feature enables optimal signal integrity as well as  
optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is  
quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for  
free at www.silabs.com/pcie-learningcenter.  
NC  
VDD  
DIFF1  
DIFF1  
25  
GND  
VSS  
14 DIFF0  
OE_DIFF0*  
VDD  
13  
DIFF0  
7
8
9
10  
11  
12  
*Note: Internal 100 kohm pull-up.  
Patents pending  
Functional Block Diagram  
DIFF0  
DIFFIN  
DIFFIN  
DIFF1  
Control & Memory  
SCLK  
SDATA  
Control  
RAM  
OE [1:0]  
Rev. 1.2 4/16  
Copyright © 2016 by Silicon Laboratories  
Si53152  
1234567...22

中文翻译

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SI53152-A01AGM 替代型号

型号 品牌 替代类型 描述 数据表
SI53152-A01AGMR SILICON

完全替代

 Low Skew Clock Driver, 53152 Series, 4 True Output(s), 0 Inverted Output(s), QFN-24

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