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SI52112-B6-GT PDF预览

SI52112-B6-GT

更新时间: 2024-11-28 19:55:35
品牌 Logo 应用领域
芯科 - SILICON 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
18页 161K
描述
Processor Specific Clock Generator, 100MHz, CMOS, PDSO8, ROHS COMPLIANT, MO-153AA, TSSOP-8

SI52112-B6-GT 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:1.23JESD-30 代码:R-PDSO-G8
长度:4.4 mm端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:100 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
主时钟/晶体标称频率:25 MHz座面最大高度:1.2 mm
最大供电电压:3.46 V最小供电电压:3.13 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

SI52112-B6-GT 数据手册

 浏览型号SI52112-B6-GT的Datasheet PDF文件第2页浏览型号SI52112-B6-GT的Datasheet PDF文件第3页浏览型号SI52112-B6-GT的Datasheet PDF文件第4页浏览型号SI52112-B6-GT的Datasheet PDF文件第5页浏览型号SI52112-B6-GT的Datasheet PDF文件第6页浏览型号SI52112-B6-GT的Datasheet PDF文件第7页 
Si52112-B5/B6  
PCI-EXPRESS GEN 3 DUAL OUTPUT CLOCK GENERATOR  
Features  
PCI-Express Gen 1, Gen 2, and Extended Temperature:  
Gen 3 compliant  
–40 to 85 °C  
Low power HCSL differential  
3.3 V Power supply  
output buffers  
Small package 10-pin TDFN  
Supports Serial-ATA (SATA) at  
(3x3 mm)  
100 MHz  
Si52112-B5 does not support  
No termination resistors required  
spread spectrum outputs  
25 MHz Crystal Input or Clock  
Si52112-B6 supports 0.5% down  
input  
spread outputs  
Ordering Information:  
Triangular spread spectrum  
profile for maximum EMI  
reduction (Si52112-B6)  
See page 12  
Pin Assignments  
Applications  
Network attached storage  
Multi-function printer  
Wireless access point  
Routers  
VDD  
1
2
3
4
5
10  
9
VDD  
DIFF2  
XOUT  
Description  
8
DIFF2  
DIFF1  
XIN/CLKIN  
VSS  
Si52112-B5/B6 is a high-performance, PCIe clock generator that can  
source two PCIe clocks from a 25 MHz crystal or clock input. The clock  
outputs are compliant to PCIe Gen 1, Gen 2, and Gen 3 specifications.  
The ultra-small footprint (3x3 mm) and industry leading low power  
consumption make Si52112-B5/B6 the ideal clock solution for consumer  
and embedded applications.  
7
VSS  
6
DIFF1  
Patents pending  
VDD  
DIFF1  
XIN/CLKIN  
XOUT  
PLL  
Divider  
DIFF2  
VSS  
Rev 1.0 4/13  
Copyright © 2013 by Silicon Laboratories  
Si52112-B5/B6  

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