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SI52112-B5-GM2 PDF预览

SI52112-B5-GM2

更新时间: 2024-11-28 19:47:31
品牌 Logo 应用领域
芯科 - SILICON 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
20页 1196K
描述
Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, 3 X 3 MM, ROHS COMPLIANT, MO-229, TDFN-10

SI52112-B5-GM2 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:HVSON,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:1.23JESD-30 代码:S-PDSO-N10
长度:3 mm端子数量:10
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:100 MHz封装主体材料:PLASTIC/EPOXY
封装代码:HVSON封装形状:SQUARE
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
主时钟/晶体标称频率:25 MHz座面最大高度:0.8 mm
最大供电电压:3.46 V最小供电电压:3.13 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

SI52112-B5-GM2 数据手册

 浏览型号SI52112-B5-GM2的Datasheet PDF文件第2页浏览型号SI52112-B5-GM2的Datasheet PDF文件第3页浏览型号SI52112-B5-GM2的Datasheet PDF文件第4页浏览型号SI52112-B5-GM2的Datasheet PDF文件第5页浏览型号SI52112-B5-GM2的Datasheet PDF文件第6页浏览型号SI52112-B5-GM2的Datasheet PDF文件第7页 
Si52112-B5/B6  
PCI-EXPRESS GEN 3 DUAL OUTPUT CLOCK GENERATOR  
Features  
PCI-Express Gen 1, Gen 2,  
Gen 3, and Gen 4 common clock  
compliant  
Triangular spread spectrum  
profile for maximum EMI  
reduction (Si52112-B6)  
Gen 3 SRNS Compliant  
Extended Temperature:  
–40 to 85 °C  
Low power HCSL differential  
output buffers  
3.3 V Power supply  
Supports Serial-ATA (SATA) at  
Small package 10-pin TDFN  
100 MHz  
(3x3 mm)  
No termination resistors required  
Si52112-B5 does not support  
Ordering Information:  
25 MHz Crystal Input or Clock  
spread spectrum outputs  
See page 13  
input  
Si52112-B6 supports 0.5% down  
spread outputs  
Pin Assignments  
Applications  
Network attached storage  
Multi-function printer  
Wireless access point  
Routers  
VDD  
1
2
3
4
5
10  
9
VDD  
DIFF2  
XOUT  
Description  
8
DIFF2  
DIFF1  
XIN/CLKIN  
VSS  
Si52112-B5/B6 is a high-performance, PCIe clock generator that can  
source two PCIe clocks from a 25 MHz crystal or clock input. The clock  
outputs are compliant to PCIe Gen 1, Gen 2, Gen 3, Gen 3 SRNS and  
Gen 4 common clock specifications. The ultra-small footprint (3x3 mm)  
and industry leading low power consumption make Si52112-B5/B6 the  
ideal clock solution for consumer and embedded applications. Measuring  
PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter  
Tool. Download it for free at www.silabs.com/pcie-learningcenter.  
7
VSS  
6
DIFF1  
Patents pending  
Functional Block Diagram  
VDD  
DIFF1  
XIN/CLKIN  
XOUT  
PLL  
Divider  
DIFF2  
VSS  
Rev 1.2 12/15  
Copyright © 2015 by Silicon Laboratories  
Si52112-B5/B6  

SI52112-B5-GM2 替代型号

型号 品牌 替代类型 描述 数据表
SI52112-B3-GM2 SILICON

完全替代

Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, 3 X 3 MM, ROHS COMPLIANT, MO-229
SI52112-B6-GM2 SILICON

完全替代

Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, 3 X 3 MM, ROHS COMPLIANT, MO-229
SI52112-A1-GM2 SILICON

完全替代

Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, 3 X 3 MM, ROHS COMPLIANT, MO-229

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