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SI4133W-BM PDF预览

SI4133W-BM

更新时间: 2024-11-19 02:58:35
品牌 Logo 应用领域
芯科 - SILICON 信号电路锁相环或频率合成电路GSM无线通信
页数 文件大小 规格书
32页 515K
描述
RF SYNTHESIZER WITH INTEGRATED VCOS FOR W-CDMA AND GSM/UMTS WIRELESS COMMUNICATIONS

SI4133W-BM 技术参数

生命周期:Obsolete包装说明:MLP-28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZERJESD-30 代码:S-XQCC-N28
长度:5 mm功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-25 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE座面最大高度:0.9 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:OTHER端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
宽度:5 mmBase Number Matches:1

SI4133W-BM 数据手册

 浏览型号SI4133W-BM的Datasheet PDF文件第2页浏览型号SI4133W-BM的Datasheet PDF文件第3页浏览型号SI4133W-BM的Datasheet PDF文件第4页浏览型号SI4133W-BM的Datasheet PDF文件第5页浏览型号SI4133W-BM的Datasheet PDF文件第6页浏览型号SI4133W-BM的Datasheet PDF文件第7页 
Si4133W  
RF SYNTHESIZER WITH INTEGRATED VCOS  
FOR W-CDMA AND GSM/UMTS WIRELESS COMMUNICATIONS  
Features  
Dual RF synthesizers  
RF1: 2.3 GHz to 2.6 GHz  
RF2: 750 MHz to 1.7 GHz  
IF synthesizer  
Continuous operation over a  
wide temperature range  
Fast settling time: 200 µsec  
Low phase noise  
IF: 62.5 MHz to 1.0 GHz  
5 µA standby current  
Ordering Information:  
Integrated VCOs, loop filters, 28-lead MLP, 5 x 5 mm  
dividers, and phase detectors  
See page 28.  
Minimal external components  
Pin Assignments  
Applications  
Si4133W-BM  
Single-mode W-CDMA wireless Dual-mode GSM/UMTS wireless  
handsets, terminals, and  
modems  
handsets, terminals, and  
modems  
GNDR  
RFLD  
RFLC  
GNDR  
NC  
GNDI  
IFLB  
Description  
IFLA  
The Si4133W is a monolithic integrated circuit that performs RF and IF  
synthesis for GSM/GPRS and W-CDMA wireless communications. In dual-  
mode GSM/UMTS handsets, the Si4133W meets demanding requirements  
for very low phase noise and fast settling time for both modes. The Si4133W  
integrates three complete phase-locked loops (PLLs) on a single die  
including VCOs, loop filters, reference and VCO dividers, and phase  
detectors. Dividers and powerdown settings are programmable through a  
three-wire serial interface.  
GNDD  
VDDD  
GNDR  
GNDR  
GNDD  
XIN  
Patents pending  
Functional Block Diagram  
Reference  
XIN  
÷R  
÷R  
÷R  
Phase  
Amplifier  
Detector  
RF1  
RF2  
IF  
Power  
Down  
PWDNB  
RFOUT  
÷N  
÷N  
÷N  
Control  
SDATA  
SCLK  
RFLC  
RFLD  
Serial  
Interface  
Phase  
Detector  
22-bit  
Data  
SENB  
Register  
Test  
Mux  
Phase  
Detector  
AUXOUT  
IFDIV  
IFOUT  
IFLA  
IFLB  
Rev. 1.1 9/02  
Copyright © 2002 by Silicon Laboratories  
Si4133W-DS11  

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