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SI4112G

更新时间： 2024-11-11 09:26:07
品牌 Logo 应用领域
芯科 - SILICON GSM无线
页数 文件大小 规格书
32页 468K
描述
DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR GSM AND GPRS WIRELESS COMMUNICATIONS

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中文翻译

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SI4112G 数据手册

 浏览型号SI4112G的Datasheet PDF文件第2页浏览型号SI4112G的Datasheet PDF文件第3页浏览型号SI4112G的Datasheet PDF文件第4页浏览型号SI4112G的Datasheet PDF文件第5页浏览型号SI4112G的Datasheet PDF文件第6页浏览型号SI4112G的Datasheet PDF文件第7页 
Si4133G  
Si4123G/22G/13G/12G  
DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS  
FOR GSM AND GPRS WIRELESS COMMUNICATIONS  
Features  
ꢀ
Dual-Band RF Synthesizers ꢀ Fast Settling Time: 140 µs  
ꢁ RF1: 900 MHz to 1.8 GHz  
ꢁ RF2: 750 MHz to 1.5 GHz  
IF Synthesizer  
ꢀ
ꢀ
ꢀ
ꢀ
Low Phase Noise  
Programmable Power Down Modes  
1 µA Standby Current  
Si4133G-BT  
ꢀ
ꢀ
ꢀ
ꢁ IF: 500 MHz to 1000 MHz  
18 mA Typical Supply Current  
Integrated VCOs, Loop Filters, ꢀ 2.7 V to 3.6 V Operation  
Varactors, and Resonators ꢀ Packages: 24-Pin TSSOP and  
Minimal External Components  
Required  
Ordering Information:  
28-Pin MLP  
See page 28.  
Applications  
Pin Assignments  
ꢀ
GSM, DCS1800, and PCS1900 ꢀ GPRS Data Terminals  
Cellular Telephones HSCSD Data Terminals  
ꢀ
Si4133G-BT  
Description  
SCLK  
SDATA  
GNDR  
RFLD  
SENB  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VDDI  
2
The Si4133G is a monolithic integrated circuit that performs both IF and  
dual-band RF synthesis for GSM and GPRS wireless communications  
applications. The Si4133G includes three VCOs, loop filters, reference and  
VCO dividers, and phase detectors. Divider and power down settings are  
programmable through a three-wire serial interface.  
IFOUT  
GNDI  
IFLB  
3
4
RFLC  
5
IFLA  
GNDR  
RFLB  
6
GNDD  
VDDD  
GNDD  
XIN  
7
RFLA  
8
Functional Block Diagram  
GNDR  
GNDR  
RFOUT  
VDDR  
9
10  
11  
12  
Reference  
Amplifier  
÷ 65  
XIN  
RFLA  
RFLB  
PWDNB  
AUXOUT  
Phase  
Detector  
RF1  
RF2  
IF  
Power  
Down  
PW DNB  
RFOUT  
÷ N  
÷ N  
÷ N  
Control  
Si4133G-BM  
SDATA  
SCLK  
RFLC  
RFLD  
Phase  
Serial  
Interface  
Detector  
22-bit  
Data  
SENB  
28  
27  
26  
25  
24  
23  
22  
Register  
1
2
3
4
5
6
7
21  
20  
19  
18  
17  
16  
15  
G NDR  
RFLD  
RFLC  
G NDR  
RFLB  
RFLA  
G NDR  
G NDI  
IFLB  
Phase  
Test  
Mux  
AUXOUT  
IFOUT  
Detector  
IFLA  
IFLA  
IFLB  
G NDD  
VDDD  
G NDD  
XIN  
8
9
10  
11  
12  
13  
14  
Patents pending  
Rev. 1.1 4/01  
Copyright © 2001 by Silicon Laboratories  
Si4133G-DS11  
1234567...32

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