SI3909DV

更新时间： 2024-11-08 21:56:07

品牌	Logo	应用领域
威世 - VISHAY		/
页数	文件大小	规格书
3页	243K
描述
Dual P-Channel 20-V (D-S) MOSFET

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技术参数
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SI3909DV 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.89	Is Samacsys：	N
最大漏极电流 (Abs) (ID)：	1.8 A	FET 技术：	METAL-OXIDE SEMICONDUCTOR
JESD-609代码：	e0	工作模式：	ENHANCEMENT MODE
最高工作温度：	150 °C	极性/信道类型：	P-CHANNEL
最大功率耗散 (Abs)：	1.15 W	子类别：	Other Transistors
表面贴装：	YES	端子面层：	Tin/Lead (Sn/Pb)
Base Number Matches：	1

SI3909DV 数据手册

SPICE Device Model Si3909DV

Vishay Siliconix

Dual P-Channel 20-V (D-S) MOSFET

CHARACTERISTICS

• P-Channel Vertical DMOS

• Macro Model (Subcircuit Model)

• Level 3 MOS

• Apply for both Linear and Switching Application

• Accurate over the −55 to 125°C Temperature Range

• Model the Gate Charge, Transient, and Diode Reverse Recovery

Characteristics

DESCRIPTION

The attached spice model describes the typical electrical

characteristics of the p-channel vertical DMOS. The subcircuit

model is extracted and optimized over the −55 to 125°C

temperature ranges under the pulsed 0-V to 5-V gate drive. The

saturated output impedance is best fit at the gate bias near the

threshold voltage.

A novel gate-to-drain feedback capacitance network is used to model

the gate charge characteristics while avoiding convergence difficulties

of the switched C_gdmodel. All model parameter values are optimized

to provide a best fit to the measured electrical data and are not

intended as an exact physical interpretation of the device.

SUBCIRCUIT MODEL SCHEMATIC

This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate

data sheet of the same number for guaranteed specification limits.

www.vishay.com

Document Number: 71511

S-50836 Rev. B, 16-May-05

12 3

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