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SG5032EAN156.250000M-KJBA0 PDF预览

SG5032EAN156.250000M-KJBA0

更新时间： 2024-11-27 09:06:51
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精工 - SEIKO /
页数 文件大小 规格书
2页 828K
描述
LVPECL Output Clock Oscillator,

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SG5032EAN156.250000M-KJBA0 数据手册

 浏览型号SG5032EAN156.250000M-KJBA0的Datasheet PDF文件第2页 
Crystal oscillator  
Product Number (please contact us)  
SG3225EAN: X1G004251xxxx00  
SG3225VAN: X1G004241xxxx00  
SG5032EAN: X1G004271xxxx00  
SG5032VAN: X1G004261xxxx00  
SG7050EAN: X1G004291xxxx00  
SG7050VAN: X1G004281xxxx00  
CRYSTAL OSCILLATOR (SPXO)  
OUTPUT : LV-PECL, LVDS  
SG3225EAN  
SG5032EAN  
SG7050EAN  
/
/
/
VAN  
VAN  
VAN  
SG3225EAN/VAN  
SG5032EAN/VAN  
SG7050EAN/VAN  
•
Achieved wide frequency range by PLL technology and AT crystal units  
(3.2 × 2.5 × 1.05 mm) (5.0 × 3.2 × 1.0 mm) (7.0 × 5.0 × 1.4 mm)  
Actual size  
•Frequency range  
•Supply voltage  
•Function  
• Output  
:
:
:
73.5 MHz to 700 MHz  
2.5 V to 3.3 V  
Output enable (OE)  
LV-PECL or LVDS  
SG5032EAN/VAN  
SG3225EAN/VAN  
SG7050EAN/VAN  
:
Specifications (characteristics)  
Specifications  
LV-PECL  
SG3225EAN / SG5032EAN /  
SG7050EAN  
LVDS  
Item  
Symbol  
Conditions / Remarks  
SG3225VAN / SG5032VAN /  
SG7050VAN  
Output frequency range  
73.5 MHz to 700 MHz  
f
0
Please contact us about available frequencies.  
Storage as single product.  
Supply voltage  
V
CC  
K: 2.5 V - 10 % to 3.3 V + 10 %  
-40 °C to +125 °C  
Storage temperature  
Operating temperature  
Frequency tolerance  
Current consumption  
Disable current  
T_stg  
T_use  
f_tol  
B: -20 °C to +70 °C, G: -40 °C to +85 °C  
J: ± 50 × 10-6, E: ± 30 × 10-6, C: ± 20 × 10-6  
I
CC  
65 mA Max.  
30 mA Max.  
OE = Vcc, L_ECL = 50 Ω or L_LVDS = 100 Ω  
OE = GND  
At outputs crossing point  
I_dis  
SYM  
20 mA Max.  
45 % to 55 %  
Symmetry  
V
V
V
OH  
OL  
OD  
dVOD  
OS  
V
CC - 1.0 V to VCC - 0.8 V  
−
−
Output voltage (LV-PECL)  
DC characteristics  
V
CC - 1.78 V to VCC - 1.62 V  
250 mV to 450 mV  
50 mV Max.  
1.15 V to 1.35 V  
150 mV Max.  
−
V
OD1, VOD2  
dVOD = | VOD1-VOD2  
OS1, VOS2  
dVOS = | VOS1-VOS2  
−
−
−
−
50 Ω  
−
|
Output voltage (LVDS)  
DC characteristics  
V
V
dVOS  
L_ECL  
L_LVDS  
|
Output load condition  
(ECL) / (LVDS)  
Terminated to VCC -2.0 V  
Connected between OUT to OUT  
100 Ω  
V
V
IH  
70 % VCC Min.  
30 % VCC Max.  
Input voltage  
OE terminal  
IL  
LV-PECL: Between 20 % and 80 % of (VOH-VOL).  
Rise time / Fall time  
tr  
/ tf  
350 ps Max.  
300 ps Max.  
LVDS:  
Between 20 % and 80 %of Differential Output  
peak to peak voltage  
Start-up time  
Phase Jitter  
t_str  
3 ms Max.  
Time at minimum supply voltage to be 0 s  
Offset frequency: 12 kHz to 20 MHz  
+25 °C, First year, VCC = 2.5 V, 3.3 V  
tPJ  
0.6 ps Max.*1  
Frequency aging  
f_aging  
± 5 × 10-6 / year Max.  
*1 0.9 ps Max. (f0 = 243 MHz ~ 250 MHz, 486 MHz ~ 500 MHz)  
Product Name  
(Standard form)  
SG3225 E AN 156.250000MHz K J G A  
(ꢀꢁ: CG is not available)  
ꢂ
ꢃ
ꢄ
ꢅꢀꢁꢆ  
ꢂModel  
ꢃOutput (E: LV-PECL, V: LVDS) ꢄFrequency ꢅSupply voltage ꢀFrequency tolerance  
ꢁOperating temperature ꢆInternal identification code (“A” is default)  
ꢅSupply voltage  
ꢁOperating temperature  
ꢀFrequency tolerance  
J
E
C
±50 × 10-6  
±30 × 10-6  
±20 × 10-6  
K
2.5 V ~ 3.3 V  
B
-20 °C ~ +70 °C  
-40 °C ~ +85 °C  
G
External dimensions  
(Unit: mm)  
Footprint (Recommended)  
(Unit: mm)  
E
B
#6  
#5  
#4  
#1  
#2  
D
#3  
Size  
SG3225 type  
1.05  
SG5032 type  
1.60  
SG7050 type  
2.00  
A
B
C
D
E
0.86  
1.85  
2.58  
0.82  
0.89  
2.60  
2.54  
0.89  
1.80  
4.20  
5.08  
1.80  
To maintain stable operation, provide a 0.01 µF to  
0.1 µF by-pass capacitor at a location as near as  
possible to the power source terminal of the  
crystal product (between Vcc - GND).  
12

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