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SG500CYB PDF预览

SG500CYB

更新时间: 2024-11-23 19:48:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
9页 61K
描述
Processor Specific Clock Generator, 133MHz, CMOS, PDSO28, 0.209 INCH, SSOP-28

SG500CYB 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:0.209 INCH, SSOP-28针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:10.2 mm湿度敏感等级:1
端子数量:28最高工作温度:70 °C
最低工作温度:最大输出时钟频率:133 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP28,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):220
电源:3.3 V主时钟/晶体标称频率:16 MHz
认证状态:Not Qualified座面最大高度:2 mm
子类别:Clock Generators最大供电电压:3.45 V
最小供电电压:3.15 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

SG500CYB 数据手册

 浏览型号SG500CYB的Datasheet PDF文件第2页浏览型号SG500CYB的Datasheet PDF文件第3页浏览型号SG500CYB的Datasheet PDF文件第4页浏览型号SG500CYB的Datasheet PDF文件第5页浏览型号SG500CYB的Datasheet PDF文件第6页浏览型号SG500CYB的Datasheet PDF文件第7页 
APPROVED PRODUCT  
SG500  
Low Jitter Spectrum Clock Generator for Power PC Designs  
Product Features  
Frequency Table  
FS2 FS1 FS0 CPU  
PCI  
30.0  
31.5  
33.3*  
35**  
33.3*  
35.0**  
30.0  
PCIF  
60.0  
63  
66.6*  
70**  
66.6*  
69.9**  
60.0  
Supports Power PC CPU’s  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
90  
Supports simultaneous PCI and Fast PCI Buses.  
Uses external buffer to reduce EMI and Jitter  
PCI synchronous clock  
94.5(90+5%)  
66.6*  
70(66+5%)*  
100.0(99.6)*  
105.0**  
Fast PCI synchronous clock  
Separated 3.3 volt power supplies for reduced Jitter  
<500 pS skew between CPU and PCI clocks  
Programmable features:  
120.0(119.9)  
133.0**  
33.3**  
66.6**  
* Indicates 0.5% down spread spectrum capable  
** See Test Mode table for functional definition when  
SSON is low.  
(TEST MODE FUNCTIONALITY NOT GUARANTEED OVER  
FULL TEMPERATURE AND VOLTAGE)  
-
-
-
-
Frequency selection  
Margin testing frequency increases  
Output enable for board level testing  
CPU to PCI clock offset selection  
Independent VDD supplies for all output clocks  
28 pin SOP 209 mil package  
Spread Spectrum Technology for EMI reduction  
Internal Crystal Load Capacitors for 20pF parallel  
resonant crystal support.  
Pin Configuration  
Block Diagram  
VDDR  
REF  
VDD  
XIN  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
REF  
14.318  
XIN  
REF  
VDDR  
XOUT  
VSS  
VDD  
FS0  
VSS  
VDDC  
CPU  
XOUT  
VSS  
VDDCPU  
CPU  
FS1  
VDDP  
PCI  
PLL1  
FS2  
VDD  
VSS  
VSS  
9
VDDPF  
VDDPF  
PCIF  
VDDPF  
48M  
OE  
10  
11  
12  
13  
14  
PCIF  
PCI  
NC  
SSON  
VSS  
VDDP  
FS(0:2)  
SSON  
OE  
VSS  
VDDF  
48MHz  
28 pin SSOP  
PLL2  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07015 Rev. **  
7/12/1998  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 1 of 9  

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