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SG-645PCW135.0000MM:PURESN PDF预览

SG-645PCW135.0000MM:PURESN

更新时间： 2024-10-28 19:15:39
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精工 - SEIKO 输出元件
页数 文件大小 规格书
2页 52K
描述
CRYSTAL OSCILLATOR, CLOCK, CMOS OUTPUT

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SG-645PCW135.0000MM:PURESN 数据手册

 浏览型号SG-645PCW135.0000MM:PURESN的Datasheet PDF文件第2页 
Crystal oscillator  
SOJ HIGH-FREQUENCY CRYSTAL OSCILLATOR  
SG-645 series  
Product number (Please refer to P1)  
Q3364 5xxxx xxx 00  
• Reflowable and high-density mounting-type SMD.  
• Operable 3.3 V or 5.0 V.  
• Output frequency from 2.5 MHz to 135 MHz.  
• Output enable (OE:P type) or Stanby (ST:S Type) function allow more low  
current consumption.  
Actual size  
Specifications  
Item  
Symbol  
Remarks  
SG-645PTG  
SG-645PHG  
2.5000 MHz to 33.0000 MHz  
-0.5 V to +7.0 V  
4.5 V to 5.5 V  
-55 °C to +125 °C  
SG-645PCG/SCG  
2.7 V to 3.6 V  
Output frequency range  
fO  
Refer to page 31. "Frequency range"  
Max. supply voltage  
Power source  
voltage  
Temperature  
range  
VDD-GND  
Operating voltage  
V
DD  
STG  
OPR  
Storage temperature  
Operating temperature  
T
Stored as bare product after unpacking  
Refer to page 31. "Frequency range"  
-20 °C to +70 °C  
T
-40 °C to +85 °C  
B : ±50 x 10-6 C : ±100 x 10-6  
M : ±100 x 10-6  
Frequency stability  
∆f/f0  
-40 °C to +85 °C  
No load condition  
OE=GND (P G)  
ST=GND (SCG)  
25 mA Max.  
20 mA Max.  
—
12 mA Max.  
10 mA Max.  
50 µA Max.  
Current consumption  
Output disable current  
Standby current  
I
I
I
OP  
OE  
ST  
50 % VDD, CL = 25 pF  
1.4 V Level, CL = 25 pF  
IOH = -8 mA  
CMOS level  
—
45 % to 55 %  
Duty  
tw/t  
TTL level  
40 % to 60 %  
2.4 V Min.  
—
—
—
VDD -0.4 V Min.  
—
VOH  
IOH = -16 mA  
IOL = 8 mA  
IOL = 16 mA  
VDD -0.4 V Min.  
Output voltage  
—
0.4 V Max.  
—
VOL  
0.4 V Max.  
Output load condition (fan out)  
CL  
VIH  
VIL  
25 pF  
Output enable  
CMOS level  
2.0 V Min.  
0.8 V Max.  
70 % VDD Min.  
20 % VDD Max.  
OE,ST  
OE,ST  
disable input voltage  
TTL level  
CMOS level  
Output rise time  
TTL level  
—
3.4 ns Max.  
4.0 ns Max.  
20 % to 80 % VDD, CL ≤ 25 pF  
0.8 V to 2.0 V CL ≤ 25 pF  
0.4 V to 2.4 V CL ≤ 25 pF  
80 % to 20 % VDD CL ≤ 25 pF  
2.0 V to 0.8 V CL ≤ 25 pF  
2.4 V to 0.4 V CL ≤ 25 pF  
Time at minimum operating voltage to be 0 s  
Ta=+25 °C, VDD = 5.5 V / 3.3 V, First year  
t
t
TLH  
THL  
1.2 ns Max.  
2.4 ns Max.  
—
1.2 ns Max.  
2.4 ns Max.  
—
—
—
—
4.0 ns Max.  
—
CMOS level  
Output fall time  
TTL level  
3.4 ns Max.  
—
—
—
12 ms Max.  
±5 x 10-6 Max.  
Oscillation start up time  
Aging  
t
OSC  
fa  
Three drops on a hard board from 750 mm or  
excitation test with 29400 m/s2 x 0.3 ms x 1/2  
sine wave in 3 directions  
±20 x 10-6  
Shock resistance  
S.R.  
Note: • Unless otherwise stated, characteristics (specifications) shown in the above table are based on the rated operating temperature and voltage condition.  
• External by-pass capacitor is recommended.  
2.5  
3.375  
3.579545  
3.6864  
3.75  
3.84  
4.0  
5.0  
6.75  
7.5  
7.68  
8.0  
10.0  
11.25  
12.288  
12.5  
13.5  
15.0  
15.36  
16.0  
20.0  
22.5  
27.0  
30.0  
30.72  
32.0  
2.8125  
3.072  
3.125  
5.625  
6.144  
6.25  
7.15909  
7.3728  
14.31818  
14.7456  
14.74945  
28.63636  
29.4912  
29.4989  
24.576  
25.0  
3.6873625  
4.096  
7.374725  
8.192  
16.384  
32.768  
(Unit: mm)  
(Unit: mm)  
7.1±0.2  
# 4  
# 3  
NO. Pin terminal  
1.8  
1
2
3
4
OE or ST  
GND  
OUT  
VDD  
# 1  
# 2  
0.4  
0 Min.  
5.08  
(0.75)  
(0.75)  
Note.  
OE Pin (PT, PH, PC, PTW, PHW, PCW)  
OE pin - "H" or "open" : Specified frequency output.  
OE pin - "L" : Output is high impedance.  
5.08  
ST pin (PT, PH, PC, PTW, PHW,PCW)  
ST pin - "H" or "open" : Specified frequency output.  
ST pin - "L" : Output is low level (weak pull-down), oscillation stops.  
39  
Metal may be exposed on the top or bottom of this product. This won't affect any quality, reliability or electrical spec.  
12

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