Datasheet > SFC2282-50WC

SFC2282-50WC

更新时间： 2024-02-18 10:09:21

品牌	Logo	应用领域
商升特 - SEMTECH		LTE
页数	文件大小	规格书
9页	247K
描述
Data Line Filter, 2 Function(s), 5V

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SFC2282-50WC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8504.50.80.00	风险等级：	5.92
电容：	100 µF	最大直流电阻：	55 Ω
滤波器类型：	DATA LINE FILTER	高度：	0.75 mm
JESD-609代码：	e0	长度：	1.47 mm
安装类型：	SURFACE MOUNT	功能数量：	2
最高工作温度：	125 °C	最低工作温度：	-55 °C
包装方法：	TAPE AND REEL	物理尺寸：	L1.47XB0.97XH0.75 (mm)
额定电压：	5 V	端子面层：	Tin/Lead (Sn/Pb)
宽度：	0.97 mm	Base Number Matches：	1

SFC2282-50WC 数据手册

SFC2282-50

ChipClamp^ΤΜ

Flip Chip TVS Diode with T-Filter

PRELIMINARY

PROTECTION PRODUCTS

Features

Description

The SFC2282-50 is a low pass filter with integrated

TVS diodes. It is designed to provide bidirectional

filtering of EMI/RFI signals and electrostatic discharge

(ESD) protection in portable electronic equipment. This

state-of-the-art device utilizes solid-state silicon-

avalanche technology for superior clamping perfor-

mance and DC electrical characteristics.

Flip Chip bidirectional EMI/RFI filter with

integrated ESD protection

ESD protection to

IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)

IEC 61000-4-4 (EFT) 40A (5/50ns)

Filter performance: attenuation 100MHz to 3GHz

Small chip scale package requires less board space

Low profile (< 0.65mm)

Each device will protect two data or I/O lines. The

device has very low insertion loss in the pass band (to

approximately 10MHz) and good attenuation at high

frequencies (approximately 100MHz to 3GHz). Each

line features two stages of TVS diode protection. The

TVS diodes form a voltage divider with the series

resistor. The voltage divider action of the circuit limits

the voltage across the protected IC to very close to the

breakdown voltage (V_BR) of the second TVS. The TVS

diodes provide effective suppression of ESD voltages

in excess of ±15kV (air discharge) and ±8kV (contact

discharge) per IEC 61000-4-2, level 4. The flip chip

design results in lower inductance, virtually eliminating

voltage overshoot due to leads and interconnecting

bond wires.

No need for underfill material

Maximum Dimensions: 1.5 x 1.0 x 0.65 mm

Protection and filtering for two lines

Working voltage: 5V

Solid-state technology

Mechanical Characteristics

JEDEC MO-211, 0.50 mm Pitch Flip Chip Package

Non-conductive top side coating

Marking : Marking Code and orientation mark

Packaging : Tape and Reel

Applications

Cell Phone Handsets and Accessories

Personal Digital Assistants (PDA’s)

Notebook and Hand Held Computers

Portable Instrumentation

Smart Cards

The SFC2282-50 is a 6-bump, 0.5mm pitch flip chip

array with a 3x2 bump grid. It measures 1.5 x 1.0 x

0.65mm. This small outline makes the SFC2282-50

especially well suited for portable applications. They

are compatible with current pick and place equipment

and assembly methods.

MP3 Players

GPS

Circuit Diagram (Each Line)

Schematic & PIN Configuration

LOW PASS FILTER

3 x 2 Grid CSP TVS (Bottom View)

www.semtech.com

Revision 09/10/04

12 3 4 5 6 7...9

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