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ACS8944EVB PDF预览

ACS8944EVB

更新时间: 2024-01-08 09:50:27
品牌 Logo 应用领域
商升特 - SEMTECH /
页数 文件大小 规格书
24页 468K
描述
Jitter Attenuating, Multiplying Phase Locked Loop for OC-12/STM-4

ACS8944EVB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN,针数:48
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.4应用程序:SONET;SDH
JESD-30 代码:S-XQCC-N48JESD-609代码:e3
长度:7 mm湿度敏感等级:1
功能数量:1端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1 mm标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

ACS8944EVB 数据手册

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ACS8944 JAM PLL  
Jitter Attenuating, Multiplying Phase Locked Loop  
for OC-12/STM-4  
ADVANCED COMMUNICATIONS  
FINAL  
DATASHEET  
Introduction  
Features  
The ACS8944 JAM PLL is a Jitter- Attenuating, Multiplying  
Phase-Locked Loop, for generating low jitter output clocks  
compliant up to SONET OC-12 and STM-4 622.08 MHz  
specifications. Its primary function is to clean up clock  
jitter for high performance optical line cards which have  
OC-3 or OC-12 SONET serializers or framers, and is the  
entry level device in Semtech’s range of JAM PLLs.  
‹ Meets rms jitter requirements of:  
‹ Telcordia GR-253-CORE[8] for OC-3 and OC-12  
‹ ITU-T G.813[4]/G.812[3] for STM-1 and STM-4 rates  
‹ ETSI EN300-462-7[1]/EN302-084[2] up to STM-16  
rates  
‹ Typical jitter generation down to:  
The ACS8944 JAM PLL has a single differential LVPECL  
input and a single differential LVPECL output. Both input  
and output clock frequencies are individually  
programmable and can be hardware configured to be any  
of 19.44 MHz, 38.88 MHz, 77.76 MHz or 155.52 MHz.  
• 0.3 ps rms for 250 kHz to 5 MHz band for G.813,  
or EN300-462, at STM-4 (OC-12) rates  
• 2.8 ps rms for 12 kHz to 20 MHz band (against  
4.02 ps rms for GR-253-CORE at OC-48 rate)  
The headline jitter figures quoted for the ACS8944  
depend on the frequency band over which the jitter is  
measured. For example, typical stand-alone output jitter  
is typically 2.8 ps rms (well within GR-253-CORE[8]  
specification requirements of 16.1 ps rms for OC-12 and  
64.3 ps rms for OC-3).  
‹ Pull-in range ±400 ppm about center input frequency  
‹ Frequency translation e.g. 19.44 MHz to 155.52 MHz  
‹ 3.3 V operation, - 40 to +85°C temperature range  
‹ Small outline leadless 7 mm x 7 mm QFN48 package  
‹ Demonstration Board available on request  
‹ PLL bandwidth and jitter peaking are fully adjustable.  
The device's operating bandwidth (and consequently the  
jitter attenuation point relating to this bandwidth) is set by  
external passive components in a differential  
‹ Supports bandwidths from 2 kHz for superior input  
jitter filtering  
arrangement which offers good noise immunity.  
‹ Lead (Pb)-free version available (ACS8944T), RoHS[9]  
and WEEE[10] compliant  
[1],[2], etc.  
Note...For items marked  
references are given in full  
Block Diagram  
in the Reference Section on page 21.  
Figure 1 Simplified Block Diagram of the ACS8944 JAM PLL  
Loop  
Filter  
RESETB  
VC  
Differential  
Input Reference  
LVPECL  
Differential  
Clock Output  
LVPECL  
PFD  
Charge  
Pump  
155.52 MHz  
77.76 MHz  
38.88 MHz  
19.44 MHz  
155.52 MHz  
77.76 MHz  
38.88 MHz  
19.44 MHz  
Frequency  
Divider  
2.5 GHz  
VCO  
Frequency  
Divider  
LVPECL  
LVPECL  
Control and Monitor  
F8944D_001Blockdiag_02  
Revision 3/November 2006 © Semtech Corp.  
Page1  
www.semtech.com  

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