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ACS8522AT PDF预览

ACS8522AT

更新时间: 2024-02-22 19:01:30
品牌 Logo 应用领域
商升特 - SEMTECH ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
118页 2149K
描述
Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems

ACS8522AT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP, QFP64,.47SQ,20针数:64
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.4Is Samacsys:N
应用程序:SONET;SDHJESD-30 代码:S-PQFP-G64
JESD-609代码:e3长度:10 mm
湿度敏感等级:3功能数量:1
端子数量:64最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP64,.47SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3,3.3/5 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Other Telecom ICs最大压摆率:0.2 mA
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
Base Number Matches:1

ACS8522AT 数据手册

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ACS8522A SETS LITE  
Synchronous Equipment Timing Source for  
Stratum 3/4E/4 and SMC Systems  
ADVANCED COMMS & SENSING  
Description  
FINAL  
Features  
DATASHEET  
The ACS8522A is a highly integrated, single-chip solution for the  
Synchronous Equipment Timing Source (SETS) function in a  
SONET or SDH Network Element. The device generates SONET  
or SDH Equipment Clocks (SEC) and Frame Synchronization  
clocks. The ACS8522A is fully compliant with the required  
international specifications and standards.  
‹ Suitable for Stratum 3, 4E, 4 and SONET Minimum  
Clock (SMC) or SONET/SDH Equipment Clock (SEC)  
applications (to Telcordia 1244-CORE[19] Stratum 3  
and GR-253[17], and ITU-T G.813[11] Options Ι and ΙΙ  
specifications).  
‹ Accepts four individual input reference clocks, all with  
The device supports Free-run, Locked and Holdover modes,  
with mode selection controlled either automatically by an  
internal state machine or forced by register configuration.  
robust input clock source quality monitoring.  
‹ Simultaneously generates four output clocks, plus two  
Sync pulse outputs.  
The ACS8522A accepts up to four independent input SEC  
reference clock sources from Recovered Line Clock, PDH  
network, and Node Synchronization. The ACS8522A generates  
independent SEC and BITS clocks, an 8 kHz Frame  
Synchronization clock and a 2 kHz Multi-Frame Synchronization  
clock, both with programmable pulse width and polarity.  
‹ Absolute Holdover accuracy better than 3 x 10-10  
(manual), 7.5 x 10-14 (instantaneous); Holdover  
stability defined by choice of external XO.  
‹ Programmable PLL bandwidth, for wander and jitter  
tracking/attenuation, 0.1 Hz to 70 Hz in 10 steps.  
The ACS8522A includes a Serial Port, which can be SPI  
compatible, providing access to the configuration and status  
registers for device setup.  
‹ Automatic hit-less source switchover on loss of input  
‹ Serial SPI compatible interface.  
[5]  
The ACS8522A supports IEEE 1149.1 JTAG boundary scan.  
‹ Output phase adjustment in 6 ps steps up to ±200 ns  
‹ IEEE 1149.1[5] JTAG Boundary Scan.  
‹ Available in LQFP 64-pin package.  
The User can choose between OCXO or TCXO to define the  
Stratum and/or Holdover performance required.  
‹ Single 3.3 V operation.  
‹ Lead (Pb)-free version available (ACS8522AT), RoHS  
Block Diagram  
and WEEE compliant.  
Figure 1 Block Diagram of the ACS8522A SETS LITE  
Output O1: PECL/LVDS  
Outputs O2 - 04: TTL  
Programmable;  
T4 DPLL/Freq. Synthesis  
E1/DS1 (2.048/  
1.544 MHz)  
and frequency  
multiples:  
1.5 x, 2 x, 3 x  
4 x, 6 x, 12 x  
16 x and 24 x  
E3/DS3  
Output  
Ports  
T4 Output  
APLL  
Digital  
Loop  
Filter  
PFD  
DTO  
Optional  
Frequency  
Dividers  
O1  
to  
O4  
T4 DPLL  
Selector  
Divider, 1/n  
Inputs: 4 x TTL  
Programmable;  
2 kHz  
4 kHz  
N x 8 kHz  
14  
n = 1 to 2  
Input  
Port  
Monitors  
and  
Selection  
Control  
2 kHz  
8 kHz  
and OC-N* rates  
1.544/2.048 MHz  
6.48 MHz  
19.44 MHz  
25.92 MHz  
38.88 MHz  
51.84 MHz  
77.76 MHz  
T0 DPLL/Freq. Synthesis  
T0 Output  
APLL  
8 kHz  
(FrSync)  
2 kHz  
4 x SEC  
FrSync  
&
MFrSync  
Frequency  
Dividers  
Optional  
T0 DPLL  
Selector  
Divider, 1/n  
(MFrSync)  
Digital  
Loop  
14  
n = 1 to 2  
PFD  
DTO  
Filter  
T0 Feedback  
APLL  
OC-N* rates =  
OC-1 51.84 MHz  
OC-3 155.52 MHz  
and derivatives:  
6.48 MHz  
19.44 MHz  
25.92 MHz  
38.88 MHz  
51.84 MHz  
TCK  
TDI  
TMS  
TRST  
TDO  
Chip  
Clock  
Generator  
IEEE  
1149.1  
JTAG  
Priority  
Table  
Serial  
Port  
Register Set  
77.76 MHz  
155.52 MHz  
311.04 MHz  
OCXO or  
TCXO  
F8522P_001BLOCKDIA_04  
Revision 1.00/September 2007 © Semtech Corp.  
Page1  
www.semtech.com  

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