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ACS8509T

更新时间： 2024-01-03 03:40:44

品牌	Logo	应用领域
商升特 - SEMTECH		ATM集成电路 SONET集成电路 SDH集成电路电信集成电路电信电路异步传输模式
页数	文件大小	规格书
68页	703K
描述
Synchronous Equipment Timing Source for SONET or SDH Network Elements

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技术参数
数据手册

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ACS8509T 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP, QFP100,.63SQ,20	针数：	100
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.42	应用程序：	SONET;SDH
JESD-30 代码：	S-PQFP-G100	JESD-609代码：	e3
长度：	14 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP100,.63SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
电源：	3.3,3.3/5 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	子类别：	ATM/SONET/SDH ICs
最大压摆率：	0.222 mA	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

ACS8509T 数据手册

ACS8509 SETS

Synchronous Equipment Timing Source for

SONET or SDH Network Elements

ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Description

Features

The ACS8509 is a highly integrated, single-chip solution

for the Synchronous Equipment Timing Source (SETS)

function in a SONET or SDH Network Element. The device

generates SONET or SDH Equipment Clocks (SEC) and

Frame Synchronization clocks. The ACS8509 is fully

compliant with the required international specifications

and standards.

Suitable for Stratum 3E*, 3, 4E, 4 and SONET

Minimum Clock (SMC) or SONET/SDH Equipment

Clock (SEC) applications

Meets AT&T, ITU-T, ETSI and Telcordia specifications

Accepts four individual input reference clocks

Generates six output clocks

Supports Free-run, Locked and Holdover modes of

The device supports Free-run, Locked and Holdover

modes. It also supports all three types of reference clock

source: recovered line clock, PDH network, and node

synchronization. The ACS8509 generates independent

SEC and BITS/SSU clocks, an 8 kHz Frame

Synchronization clock and a 2 kHz Multi-Frame

Synchronization clock.

operation

Robust input clock source quality monitoring on all

inputs

Automatic “hit-less” source switchover on loss of input

Phase build-out for output clock phase continuity

during input switchover and mode transitions

Microprocessor interface - Intel, Motorola, Serial,

Multiplexed, EPROM

Programmable wander and jitter tracking attenuation

0.1 Hz to 20 Hz

Support for Master/Slave device configuration

alignment and hot/standby redundancy

IEEE 1149.1 JTAG Boundary Scan

Two ACS8509 devices can be used together in a Master/

Slave configuration mode allowing system protection

against a single ACS8509 failure.

A microprocessor port is incorporated, providing access to

the configuration and status registers for device setup

and monitoring.

The ACS8509 includes a choice of edge alignment for

8 kHz input, as well as a low jitter n x E1/DS1 output

mode. The User can choose between OCXO or TCXO to

define the Stratum and/or Holdover performance

required.

Single +3.3 V operation, +5 V I/O compatible

Operating temperature (ambient) -40°C to +85°C

Available in 100 pin LQFP package.

Lead (Pb)-free version available (ACS8509T), RoHS

and WEEE compliant.

Block Diagram

Note...* Meets holdover requirements, lowest bandwidth 0.1 Hz.

Figure 1 Block Diagram of the ACS8509 SETS

Programmable Outputs:

T4 DPLL/Freq. Synthesis

01 (PECL (default)/LVDS) =

Programmable: 19.44 MHz (default),

51.84 MHz (OC-1), 77.76 MHz and

155.52 MHz (OC-3)

Digital

Loop

Filter

T_OUT4

Divider

PFD

DTO

02 (TTL/CMOS) = 6.48 MHz (default)

19.44 MHz and 25.92 MHz,

and E1/DS1 multiples:

Selector

4 x TTL

Programmable;

Input

Port

1 x, 2 x, 4 x, 8 x (1.544/2.048 MHz)

2 kHz

4 kHz

Monitors

and

Selection

Control

03 (TTL/CMOS) = 19.44 MHz (fixed)

6 x

Output

Ports

N x 8 kHz

1.544/2.048 MHz

6.48 MHz

19.44 MHz

25.92 MHz

38.88 MHz

51.84 MHz

77.76 MHz

04 (TTL/CMOS) =

1.544 MHz/2.048 MHz (E1/DS1)

T0 DPLL/Freq. Synthesis

4 x SEC

T0 APLL

(output)

Digital

Loop

Filter

FrSync (TTL/CMOS) =

8 kHz Frame Sync,

Fixed 50:50 MSR

T_OUT0

Selecor

DTO

PFD

Divider

Frequency

Dividers

MFrSync (TTL/CMOS) =

2 kHz Multiframe Sync,

Fixed 50:50 MSR

TCK

TDI

TMS

TRST

TDO

Chip

Clock

Generator

IEEE

1149.1

JTAG

Priority

Table

Microprocessor

Port

OCXO or

TCXO

Page1

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与ACS8509T相关器件

型号	品牌	描述	获取价格	数据表
ACS8510	SEMTECH	Synchronous Equipment Timing Source for SONET or SDH Network Elements	获取价格
ACS8510_03	SEMTECH	Synchronous Equipment Timing Source for SONET or SDH Network Elements	获取价格
ACS8510REV2.1	SEMTECH	Synchronous Equipment Timing Source for SONET or SDH Network Elements	获取价格
ACS8510REV2.1SETS	ETC	Synchronous Equipment Timing Source for SONET or SDH Network Elements	获取价格
ACS8510REV2.1T	SEMTECH	Support Circuit,	获取价格
ACS8510T	SEMTECH	暂无描述	获取价格

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