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SDA2526

更新时间： 2024-10-26 22:40:31
品牌 Logo 应用领域
英飞凌 - INFINEON 存储内存集成电路光电二极管双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 277K
描述
Nonvolatile Memory 2-Kbit E2PROM with I2C Bus

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中文翻译

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SDA2526 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP8,.3Reach Compliance Code：unknown
风险等级：5.88数据保留时间-最小值：10
耐久性：10000 Write/Erase CyclesI2C控制字节：1010DDDR
JESD-30 代码：R-PDIP-T8JESD-609代码：e0
内存密度：2048 bit内存集成电路类型：EEPROM
内存宽度：8端子数量：8
字数：256 words字数代码：256
最高工作温度：70 °C最低工作温度：
组织：256X8封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP8,.3
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：SERIAL电源：5 V
认证状态：Not Qualified串行总线类型：I2C
最大待机电流：0.01 A子类别：EEPROMs
最大压摆率：0.01 mA标称供电电压 (Vsup)：5 V
表面贴装：NO技术：MOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUALBase Number Matches：1

SDA2526 数据手册

 浏览型号SDA2526的Datasheet PDF文件第2页浏览型号SDA2526的Datasheet PDF文件第3页浏览型号SDA2526的Datasheet PDF文件第4页浏览型号SDA2526的Datasheet PDF文件第5页浏览型号SDA2526的Datasheet PDF文件第6页浏览型号SDA2526的Datasheet PDF文件第7页 
Nonvolatile Memory 2-Kbit E2PROM  
with I2C Bus  
SDA 2526-5  
Preliminary Data  
MOS IC  
Features  
● Word-organized programmable nonvolatile memory in  
2
n-channel floating-gate technology (E PROM)  
● 256 × 8-bit organization  
● Supply voltage 5 V  
● Serial 2-line bus for data input and output (I C Bus)  
2
● Reprogramming mode, 10 ms erase/write cycle  
● Reprogramming by means of on-chip control (without  
external control)  
P-DIP-8-1  
● Check for end of programming process  
● Data retention > 10 years  
4
● More than 10 reprogramming cycles per address  
● Compatible with SDA 2526. Exceptions: Conditions for  
total erase and current consumption ICC  
Type  
Ordering Code  
Package  
SDA 2526-5  
Q67100-H5095  
P-DIP-8-1  
Circuit Description  
2
I C Bus Interface  
2
The I C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.  
It consists of a serial data line SDA and a serial clock line SCL. The data line requires an external  
pull-up resistor to VCC (open drain output stage).  
2
The possible operational states of the I C Bus are shown in figure 1. In the quiescent state, both  
lines SDA and SCL are high, i.e. the output stage of the data line is disabled. As long a SCL remains  
"1", information changes on the data bus indicate the start or the end of data transfer between two  
components.  
The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" is a stop  
condition. During a data transfer the information on the data bus will only change while the clock line  
SCL is "0". The information on SDA is valid as long as SCL is "1".  
2
In conjunction with an I C Bus system, the memory component can operate as a receiver and as a  
transmitter (slave receiver or slave transmitter). Between a start and stop condition, information is  
always transmitted in byte-organized form. Between the falling edge of the eighth clock pulse and  
a ninth acknowledge clock pulse, the memory component sets the SDA-line to low as a confirmation  
of reception, if the chip select conditions have been met. During the output of data, the data output  
of the memory is high in impedance during the ninth clock pulse (acknowledge master).  
2
The signal timing required for the operation of the I C Bus is summarized in figure 2.  
Semiconductor Group  
17  
07.94  
1234567...12

中文翻译

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 		10 AMPS 70 nsec ULTRA FAST RECOVERY SINGLE PHASE BRIDGE ASSEMBLY
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 		Nonvolatile Memory 4-Kbit E2PROM with I2C Bus Interface

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