Datasheet > SCG102B-DFC-A1E4

SCG102B-DFC-A1E4

更新时间： 2024-11-13 04:33:55

品牌	Logo	应用领域
CONNOR-WINFIELD		/
页数	文件大小	规格书
8页	220K
描述
PLL/Frequency Synthesis Circuit

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SCG102B-DFC-A1E4 数据手册

SCG102B

Synchronous Clock

Generators

PLL

2111 Comprehensive Drive

Aurora, Illinois 60505

Phone: 630-851-4722

Fax: 630- 851-5040

www.conwin.com

Applications

• SONET / SDH / ATM

• DWDM / FDM

• DSL-PON Interconnects

• FEC (Forward Error Correction)

Features

• 3.3V High Precision PLL

• Accepts 1 of 4 Selectable, Pre-determined Input Frequencies

• 77.76 MHz to 170 MHz Output Frequencies Available.

• Jitter Generation OC-192 Compliant

• 1.0” x 0.80” x 0.285”, Surface Mount

• 35 - 105 Hz Jitter Bandwidth

Bulletin

SG098

Page

1 of 8

Revision

P00

Date

16 MAY 05

Issued By

ENG

12 3 4 5 6 7 8

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